1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/types.h> 9 #include <asm/arch/cru_rk3036.h> 10 #include <asm/arch/grf_rk3036.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/sdram_rk3036.h> 13 #include <asm/arch/timer.h> 14 #include <asm/arch/uart.h> 15 16 /* 17 * we can not fit the code to access the device tree in SPL 18 * (due to 4K SRAM size limits), so these are hard-coded 19 */ 20 #define CRU_BASE 0x20000000 21 #define GRF_BASE 0x20008000 22 #define DDR_PHY_BASE 0x2000a000 23 #define DDR_PCTL_BASE 0x20004000 24 #define CPU_AXI_BUS_BASE 0x10128000 25 26 struct rk3036_sdram_priv { 27 struct rk3036_cru *cru; 28 struct rk3036_grf *grf; 29 struct rk3036_ddr_phy *phy; 30 struct rk3036_ddr_pctl *pctl; 31 struct rk3036_service_sys *axi_bus; 32 33 /* ddr die config */ 34 struct rk3036_ddr_config ddr_config; 35 }; 36 37 /* 38 * use integer mode, dpll output 792MHz and ddr get 396MHz 39 * refdiv, fbdiv, postdiv1, postdiv2 40 */ 41 const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; 42 43 /* 396Mhz ddr timing */ 44 const struct rk3036_ddr_timing ddr_timing = {0x18c, 45 {0x18c, 0xc8, 0x1f4, 0x27, 0x4e, 46 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04, 47 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03, 48 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0}, 49 {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60}, 50 {0x24717315} }; 51 52 /* 53 * [7:6] bank(n:n bit bank) 54 * [5:4] row(13+n) 55 * [3] cs(0:1 cs, 1:2 cs) 56 * [2:1] bank(n:n bit bank) 57 * [0] col(10+n) 58 */ 59 const char ddr_cfg_2_rbc[] = { 60 ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1), 61 ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0), 62 ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0), 63 ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0), 64 ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1), 65 ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1), 66 ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1), 67 ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0), 68 ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1), 69 ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0), 70 ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1), 71 ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0), 72 ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1), 73 ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0), 74 }; 75 76 /* DDRPHY REG */ 77 enum { 78 /* DDRPHY_REG1 */ 79 SOFT_RESET_MASK = 3, 80 SOFT_RESET_SHIFT = 2, 81 82 /* DDRPHY_REG2 */ 83 MEMORY_SELECT_DDR3 = 0 << 6, 84 DQS_SQU_CAL_NORMAL_MODE = 0 << 1, 85 DQS_SQU_CAL_START = 1 << 0, 86 DQS_SQU_NO_CAL = 0 << 0, 87 88 /* DDRPHY_REG2A */ 89 CMD_DLL_BYPASS = 1 << 4, 90 CMD_DLL_BYPASS_DISABLE = 0 << 4, 91 HIGH_8BIT_DLL_BYPASS = 1 << 3, 92 HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3, 93 LOW_8BIT_DLL_BYPASS = 1 << 2, 94 LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2, 95 96 /* DDRPHY_REG19 */ 97 CMD_FEEDBACK_ENABLE = 1 << 5, 98 CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4, 99 CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4, 100 CMD_SLAVE_DLL_ENALBE = 1 << 3, 101 CMD_TX_SLAVE_DLL_DELAY_MASK = 7, 102 CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0, 103 104 /* DDRPHY_REG6 */ 105 LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, 106 LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, 107 LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, 108 LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7, 109 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, 110 111 /* DDRPHY_REG8 */ 112 LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3, 113 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, 114 115 /* DDRPHY_REG9 */ 116 RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, 117 RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, 118 RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, 119 RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7, 120 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, 121 122 /* DDRPHY_REG11 */ 123 RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3, 124 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, 125 126 /* DDRPHY_REG62 */ 127 CAL_DONE_MASK = 3, 128 HIGH_8BIT_CAL_DONE = 1 << 1, 129 LOW_8BIT_CAL_DONE = 1 << 0, 130 }; 131 132 /* PTCL */ 133 enum { 134 /* PCTL_DFISTCFG0 */ 135 DFI_INIT_START = 1 << 0, 136 DFI_DATA_BYTE_DISABLE_EN = 1 << 2, 137 138 /* PCTL_DFISTCFG1 */ 139 DFI_DRAM_CLK_SR_EN = 1 << 0, 140 DFI_DRAM_CLK_DPD_EN = 1 << 1, 141 142 /* PCTL_DFISTCFG2 */ 143 DFI_PARITY_INTR_EN = 1 << 0, 144 DFI_PARITY_EN = 1 << 1, 145 146 /* PCTL_DFILPCFG0 */ 147 TLP_RESP_TIME_SHIFT = 16, 148 LP_SR_EN = 1 << 8, 149 LP_PD_EN = 1 << 0, 150 151 /* PCTL_DFIODTCFG */ 152 RANK0_ODT_WRITE_SEL = 1 << 3, 153 RANK1_ODT_WRITE_SEL = 1 << 11, 154 155 /* PCTL_DFIODTCFG1 */ 156 ODT_LEN_BL8_W_SHIFT = 16, 157 158 /* PCTL_MCFG */ 159 TFAW_CFG_MASK = 3, 160 TFAW_CFG_SHIFT = 18, 161 PD_EXIT_SLOW_MODE = 0 << 17, 162 PD_ACTIVE_POWER_DOWN = 1 << 16, 163 PD_IDLE_MASK = 0xff, 164 PD_IDLE_SHIFT = 8, 165 MEM_BL4 = 0 << 0, 166 MEM_BL8 = 1 << 0, 167 168 /* PCTL_MCFG1 */ 169 HW_EXIT_IDLE_EN_MASK = 1, 170 HW_EXIT_IDLE_EN_SHIFT = 31, 171 SR_IDLE_MASK = 0x1ff, 172 SR_IDLE_SHIFT = 0, 173 174 /* PCTL_SCFG */ 175 HW_LOW_POWER_EN = 1 << 0, 176 177 /* PCTL_POWCTL */ 178 POWER_UP_START = 1 << 0, 179 180 /* PCTL_POWSTAT */ 181 POWER_UP_DONE = 1 << 0, 182 183 /* PCTL_MCMD */ 184 START_CMD = 1 << 31, 185 BANK_ADDR_MASK = 7, 186 BANK_ADDR_SHIFT = 17, 187 CMD_ADDR_MASK = 0x1fff, 188 CMD_ADDR_SHIFT = 4, 189 DESELECT_CMD = 0, 190 PREA_CMD, 191 REF_CMD, 192 MRS_CMD, 193 ZQCS_CMD, 194 ZQCL_CMD, 195 RSTL_CMD, 196 MRR_CMD = 8, 197 198 /* PCTL_STAT */ 199 INIT_MEM = 0, 200 CONFIG, 201 CONFIG_REQ, 202 ACCESS, 203 ACCESS_REQ, 204 LOW_POWER, 205 LOW_POWER_ENTRY_REQ, 206 LOW_POWER_EXIT_REQ, 207 PCTL_STAT_MASK = 7, 208 209 /* PCTL_SCTL */ 210 INIT_STATE = 0, 211 CFG_STATE = 1, 212 GO_STATE = 2, 213 SLEEP_STATE = 3, 214 WAKEUP_STATE = 4, 215 }; 216 217 /* GRF_SOC_CON2 */ 218 #define MSCH4_MAINDDR3 (1 << 7) 219 #define PHY_DRV_ODT_SET(n) ((n << 4) | n) 220 #define DDR3_DLL_RESET (1 << 8) 221 222 /* CK pull up/down driver strength control */ 223 enum { 224 PHY_RON_DISABLE = 0, 225 PHY_RON_309OHM = 1, 226 PHY_RON_155OHM, 227 PHY_RON_103OHM = 3, 228 PHY_RON_63OHM = 5, 229 PHY_RON_45OHM = 7, 230 PHY_RON_77OHM, 231 PHY_RON_62OHM, 232 PHY_RON_52OHM, 233 PHY_RON_44OHM, 234 PHY_RON_39OHM, 235 PHY_RON_34OHM, 236 PHY_RON_31OHM, 237 PHY_RON_28OHM, 238 }; 239 240 /* DQ pull up/down control */ 241 enum { 242 PHY_RTT_DISABLE = 0, 243 PHY_RTT_861OHM = 1, 244 PHY_RTT_431OHM, 245 PHY_RTT_287OHM, 246 PHY_RTT_216OHM, 247 PHY_RTT_172OHM, 248 PHY_RTT_145OHM, 249 PHY_RTT_124OHM, 250 PHY_RTT_215OHM, 251 PHY_RTT_144OHM = 0xa, 252 PHY_RTT_123OHM, 253 PHY_RTT_108OHM, 254 PHY_RTT_96OHM, 255 PHY_RTT_86OHM, 256 PHY_RTT_78OHM, 257 }; 258 259 /* DQS squelch DLL delay */ 260 enum { 261 DQS_DLL_NO_DELAY = 0, 262 DQS_DLL_22P5_DELAY, 263 DQS_DLL_45_DELAY, 264 DQS_DLL_67P5_DELAY, 265 DQS_DLL_90_DELAY, 266 DQS_DLL_112P5_DELAY, 267 DQS_DLL_135_DELAY, 268 DQS_DLL_157P5_DELAY, 269 }; 270 271 /* GRF_OS_REG1 */ 272 enum { 273 /* 274 * 000: lpddr 275 * 001: ddr 276 * 010: ddr2 277 * 011: ddr3 278 * 100: lpddr2-s2 279 * 101: lpddr2-s4 280 * 110: lpddr3 281 */ 282 DDR_TYPE_MASK = 7, 283 DDR_TYPE_SHIFT = 13, 284 285 /* 0: 1 chn, 1: 2 chn */ 286 DDR_CHN_CNT_SHIFT = 12, 287 288 /* 0: 1 rank, 1: 2 rank */ 289 DDR_RANK_CNT_MASK = 1, 290 DDR_RANK_CNT_SHIFT = 11, 291 292 /* 293 * 00: 9col 294 * 01: 10col 295 * 10: 11col 296 * 11: 12col 297 */ 298 DDR_COL_MASK = 3, 299 DDR_COL_SHIFT = 9, 300 301 /* 0: 8 bank, 1: 4 bank*/ 302 DDR_BANK_MASK = 1, 303 DDR_BANK_SHIFT = 8, 304 305 /* 306 * 00: 13 row 307 * 01: 14 row 308 * 10: 15 row 309 * 11: 16 row 310 */ 311 DDR_CS0_ROW_MASK = 3, 312 DDR_CS0_ROW_SHIFT = 6, 313 DDR_CS1_ROW_MASK = 3, 314 DDR_CS1_ROW_SHIFT = 4, 315 316 /* 317 * 00: 32 bit 318 * 01: 16 bit 319 * 10: 8 bit 320 * rk3036 only support 16bit 321 */ 322 DDR_BW_MASK = 3, 323 DDR_BW_SHIFT = 2, 324 DDR_DIE_BW_MASK = 3, 325 DDR_DIE_BW_SHIFT = 0, 326 }; 327 328 static void rkdclk_init(struct rk3036_sdram_priv *priv) 329 { 330 struct rk3036_pll *pll = &priv->cru->pll[1]; 331 332 /* pll enter slow-mode */ 333 rk_clrsetreg(&priv->cru->cru_mode_con, 334 DPLL_MODE_MASK << DPLL_MODE_SHIFT, 335 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 336 337 /* use integer mode */ 338 rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 339 340 rk_clrsetreg(&pll->con0, 341 PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, 342 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | 343 dpll_init_cfg.fbdiv); 344 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | 345 PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, 346 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | 347 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); 348 349 /* waiting for pll lock */ 350 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 351 rockchip_udelay(1); 352 353 /* PLL enter normal-mode */ 354 rk_clrsetreg(&priv->cru->cru_mode_con, 355 DPLL_MODE_MASK << DPLL_MODE_SHIFT, 356 DPLL_MODE_NORM << DPLL_MODE_SHIFT); 357 } 358 359 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 360 { 361 int i; 362 363 for (i = 0; i < n / sizeof(u32); i++) { 364 writel(*src, dest); 365 src++; 366 dest++; 367 } 368 } 369 370 void phy_pctrl_reset(struct rk3036_sdram_priv *priv) 371 { 372 struct rk3036_ddr_phy *ddr_phy = priv->phy; 373 374 rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 375 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 376 1 << DDRPHY_SRST_SHIFT, 377 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 378 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); 379 380 rockchip_udelay(10); 381 382 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 383 1 << DDRPHY_SRST_SHIFT); 384 rockchip_udelay(10); 385 386 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 387 1 << DDRCTRL_SRST_SHIFT); 388 rockchip_udelay(10); 389 390 clrsetbits_le32(&ddr_phy->ddrphy_reg1, 391 SOFT_RESET_MASK << SOFT_RESET_SHIFT, 392 0 << SOFT_RESET_SHIFT); 393 rockchip_udelay(10); 394 clrsetbits_le32(&ddr_phy->ddrphy_reg1, 395 SOFT_RESET_MASK << SOFT_RESET_SHIFT, 396 3 << SOFT_RESET_SHIFT); 397 398 rockchip_udelay(1); 399 } 400 401 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) 402 { 403 struct rk3036_ddr_phy *ddr_phy = priv->phy; 404 405 if (freq < ddr_timing.freq) { 406 writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS | 407 LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); 408 409 writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 | 410 LEFT_CHN_TX_DQ_DLL_ENABLE | 411 (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << 412 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); 413 414 writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 | 415 RIGHT_CHN_TX_DQ_DLL_ENABLE | 416 (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << 417 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, 418 &ddr_phy->ddrphy_reg9); 419 } else { 420 writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE | 421 LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); 422 423 writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 | 424 LEFT_CHN_TX_DQ_DLL_ENABLE | 425 (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << 426 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, 427 &ddr_phy->ddrphy_reg6); 428 429 writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 | 430 RIGHT_CHN_TX_DQ_DLL_ENABLE | 431 (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << 432 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, 433 &ddr_phy->ddrphy_reg9); 434 } 435 436 writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE | 437 (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) << 438 CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); 439 440 /* 45 degree delay */ 441 writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) << 442 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); 443 writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) << 444 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); 445 } 446 447 static void send_command(struct rk3036_ddr_pctl *pctl, 448 u32 rank, u32 cmd, u32 arg) 449 { 450 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); 451 rockchip_udelay(1); 452 while (readl(&pctl->mcmd) & START_CMD) 453 ; 454 } 455 456 static void memory_init(struct rk3036_sdram_priv *priv) 457 { 458 struct rk3036_ddr_pctl *pctl = priv->pctl; 459 460 send_command(pctl, 3, DESELECT_CMD, 0); 461 rockchip_udelay(1); 462 send_command(pctl, 3, PREA_CMD, 0); 463 send_command(pctl, 3, MRS_CMD, 464 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 465 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << 466 CMD_ADDR_SHIFT); 467 468 send_command(pctl, 3, MRS_CMD, 469 (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 470 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << 471 CMD_ADDR_SHIFT); 472 473 send_command(pctl, 3, MRS_CMD, 474 (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 475 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << 476 CMD_ADDR_SHIFT); 477 478 send_command(pctl, 3, MRS_CMD, 479 (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 480 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << 481 CMD_ADDR_SHIFT | DDR3_DLL_RESET); 482 483 send_command(pctl, 3, ZQCL_CMD, 0); 484 } 485 486 static void data_training(struct rk3036_sdram_priv *priv) 487 { 488 struct rk3036_ddr_phy *ddr_phy = priv->phy; 489 struct rk3036_ddr_pctl *pctl = priv->pctl; 490 u32 value; 491 492 /* disable auto refresh */ 493 value = readl(&pctl->trefi), 494 writel(0, &pctl->trefi); 495 496 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, 497 DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); 498 499 rockchip_udelay(1); 500 while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != 501 (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { 502 ; 503 } 504 505 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, 506 DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL); 507 508 /* 509 * since data training will take about 20us, so send some auto 510 * refresh(about 7.8us) to complement the lost time 511 */ 512 send_command(pctl, 3, REF_CMD, 0); 513 send_command(pctl, 3, REF_CMD, 0); 514 send_command(pctl, 3, REF_CMD, 0); 515 516 writel(value, &pctl->trefi); 517 } 518 519 static void move_to_config_state(struct rk3036_sdram_priv *priv) 520 { 521 unsigned int state; 522 struct rk3036_ddr_pctl *pctl = priv->pctl; 523 524 while (1) { 525 state = readl(&pctl->stat) & PCTL_STAT_MASK; 526 switch (state) { 527 case LOW_POWER: 528 writel(WAKEUP_STATE, &pctl->sctl); 529 while ((readl(&pctl->stat) & PCTL_STAT_MASK) 530 != ACCESS) 531 ; 532 /* 533 * If at low power state, need wakeup first, and then 534 * enter the config, so fallthrough 535 */ 536 case ACCESS: 537 /* fallthrough */ 538 case INIT_MEM: 539 writel(CFG_STATE, &pctl->sctl); 540 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) 541 ; 542 break; 543 case CONFIG: 544 return; 545 default: 546 break; 547 } 548 } 549 } 550 551 static void move_to_access_state(struct rk3036_sdram_priv *priv) 552 { 553 unsigned int state; 554 struct rk3036_ddr_pctl *pctl = priv->pctl; 555 556 while (1) { 557 state = readl(&pctl->stat) & PCTL_STAT_MASK; 558 switch (state) { 559 case LOW_POWER: 560 writel(WAKEUP_STATE, &pctl->sctl); 561 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) 562 ; 563 break; 564 case INIT_MEM: 565 writel(CFG_STATE, &pctl->sctl); 566 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) 567 ; 568 /* fallthrough */ 569 case CONFIG: 570 writel(GO_STATE, &pctl->sctl); 571 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) 572 ; 573 break; 574 case ACCESS: 575 return; 576 default: 577 break; 578 } 579 } 580 } 581 582 static void pctl_cfg(struct rk3036_sdram_priv *priv) 583 { 584 struct rk3036_ddr_pctl *pctl = priv->pctl; 585 u32 burst_len; 586 u32 reg; 587 588 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); 589 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); 590 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 591 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 592 &pctl->dfilpcfg0); 593 594 writel(1, &pctl->dfitphyupdtype0); 595 writel(0x0d, &pctl->dfitphyrdlat); 596 597 /* cs0 and cs1 write odt enable */ 598 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), 599 &pctl->dfiodtcfg); 600 601 /* odt write length */ 602 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 603 604 /* phyupd and ctrlupd disabled */ 605 writel(0, &pctl->dfiupdcfg); 606 607 if ((ddr_timing.noc_timing.burstlen << 1) == 4) 608 burst_len = MEM_BL4; 609 else 610 burst_len = MEM_BL8; 611 612 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, 613 sizeof(struct rk3036_pctl_timing)); 614 reg = readl(&pctl->tcl); 615 writel(reg - 3, &pctl->dfitrddataen); 616 reg = readl(&pctl->tcwl); 617 writel(reg - 1, &pctl->dfitphywrlat); 618 619 writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT | 620 PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN | 621 (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT, 622 &pctl->mcfg); 623 624 writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2); 625 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); 626 } 627 628 static void phy_cfg(struct rk3036_sdram_priv *priv) 629 { 630 struct rk3036_ddr_phy *ddr_phy = priv->phy; 631 struct rk3036_service_sys *axi_bus = priv->axi_bus; 632 633 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); 634 writel(0x3f, &axi_bus->readlatency); 635 636 writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE, 637 &ddr_phy->ddrphy_reg2); 638 639 clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); 640 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); 641 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); 642 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); 643 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); 644 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); 645 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); 646 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); 647 } 648 649 void dram_cfg_rbc(struct rk3036_sdram_priv *priv) 650 { 651 char noc_config; 652 int i = 0; 653 struct rk3036_ddr_config config = priv->ddr_config; 654 struct rk3036_service_sys *axi_bus = priv->axi_bus; 655 656 move_to_config_state(priv); 657 658 /* 2bit in BIT1, 2 */ 659 if (config.rank == 2) { 660 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | 661 1 << 3 | (config.col - 10); 662 if (noc_config == ddr_cfg_2_rbc[9]) { 663 i = 9; 664 goto finish; 665 } else if (noc_config == ddr_cfg_2_rbc[10]) { 666 i = 10; 667 goto finish; 668 } 669 } 670 671 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | 672 (config.col - 10); 673 674 for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) { 675 if (noc_config == ddr_cfg_2_rbc[i]) 676 goto finish; 677 } 678 679 /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */ 680 noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | 681 2 << 1 | (config.col - 10); 682 if (noc_config == ddr_cfg_2_rbc[11]) { 683 i = 11; 684 goto finish; 685 } 686 687 /* bank: 2bit in BIT6,7 */ 688 noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | 689 (config.col - 10); 690 691 if (noc_config == ddr_cfg_2_rbc[0]) 692 i = 0; 693 else if (noc_config == ddr_cfg_2_rbc[12]) 694 i = 12; 695 else if (noc_config == ddr_cfg_2_rbc[13]) 696 i = 13; 697 finish: 698 writel(i, &axi_bus->ddrconf); 699 move_to_access_state(priv); 700 } 701 702 static void sdram_all_config(struct rk3036_sdram_priv *priv) 703 { 704 u32 os_reg = 0; 705 u32 cs1_row = 0; 706 struct rk3036_ddr_config config = priv->ddr_config; 707 708 if (config.rank > 1) 709 cs1_row = config.cs1_row - 13; 710 711 os_reg = config.ddr_type << DDR_TYPE_SHIFT | 712 0 << DDR_CHN_CNT_SHIFT | 713 (config.rank - 1) << DDR_RANK_CNT_SHIFT | 714 (config.col - 9) << DDR_COL_SHIFT | 715 (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT | 716 (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | 717 cs1_row << DDR_CS1_ROW_SHIFT | 718 1 << DDR_BW_SHIFT | 719 (2 >> config.bw) << DDR_DIE_BW_SHIFT; 720 writel(os_reg, &priv->grf->os_reg[1]); 721 } 722 723 size_t sdram_size(void) 724 { 725 u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; 726 struct rk3036_grf *grf = (void *)GRF_BASE; 727 728 os_reg = readl(&grf->os_reg[1]); 729 730 cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK); 731 cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK); 732 col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK); 733 bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK); 734 rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); 735 736 /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */ 737 size = 1 << (cs0_row + col + bank + 1); 738 739 if (rank > 1) 740 size += size >> (cs0_row - cs1_row); 741 742 return size; 743 } 744 745 void sdram_init(void) 746 { 747 struct rk3036_sdram_priv sdram_priv; 748 749 sdram_priv.cru = (void *)CRU_BASE; 750 sdram_priv.grf = (void *)GRF_BASE; 751 sdram_priv.phy = (void *)DDR_PHY_BASE; 752 sdram_priv.pctl = (void *)DDR_PCTL_BASE; 753 sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE; 754 755 get_ddr_config(&sdram_priv.ddr_config); 756 sdram_all_config(&sdram_priv); 757 rkdclk_init(&sdram_priv); 758 phy_pctrl_reset(&sdram_priv); 759 phy_dll_bypass_set(&sdram_priv, ddr_timing.freq); 760 pctl_cfg(&sdram_priv); 761 phy_cfg(&sdram_priv); 762 writel(POWER_UP_START, &sdram_priv.pctl->powctl); 763 while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE)) 764 ; 765 memory_init(&sdram_priv); 766 move_to_config_state(&sdram_priv); 767 data_training(&sdram_priv); 768 move_to_access_state(&sdram_priv); 769 dram_cfg_rbc(&sdram_priv); 770 } 771