xref: /openbmc/u-boot/arch/arm/mach-rockchip/Kconfig (revision b32ba6f12e4584b85c55c89000b0ef3fd98473f5)
1if ARCH_ROCKCHIP
2
3config ROCKCHIP_RK3036
4	bool "Support Rockchip RK3036"
5	select CPU_V7A
6	select SUPPORT_SPL
7	select SPL
8	imply USB_FUNCTION_ROCKUSB
9	imply CMD_ROCKUSB
10	help
11	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12	  including NEON and GPU, Mali-400 graphics, several DDR3 options
13	  and video codec support. Peripherals include Gigabit Ethernet,
14	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
16config ROCKCHIP_RK3128
17	bool "Support Rockchip RK3128"
18	select CPU_V7A
19	help
20	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21	  including NEON and GPU, Mali-400 graphics, several DDR3 options
22	  and video codec support. Peripherals include Gigabit Ethernet,
23	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
25config ROCKCHIP_RK3188
26	bool "Support Rockchip RK3188"
27	select CPU_V7A
28	select SPL_BOARD_INIT if SPL
29	select SUPPORT_SPL
30	select SPL
31	select SPL_CLK
32	select SPL_PINCTRL
33	select SPL_REGMAP
34	select SPL_SYSCON
35	select SPL_RAM
36	select SPL_DRIVERS_MISC_SUPPORT
37	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
38	select DEBUG_UART_BOARD_INIT
39	select BOARD_LATE_INIT
40	select ROCKCHIP_BROM_HELPER
41	help
42	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
43	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44	  video interfaces, several memory options and video codec support.
45	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
46	  UART, SPI, I2C and PWMs.
47
48config ROCKCHIP_RK322X
49	bool "Support Rockchip RK3228/RK3229"
50	select CPU_V7A
51	select SUPPORT_SPL
52	select SPL
53	select ROCKCHIP_BROM_HELPER
54	select DEBUG_UART_BOARD_INIT
55	help
56	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
57	  including NEON and GPU, Mali-400 graphics, several DDR3 options
58	  and video codec support. Peripherals include Gigabit Ethernet,
59	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
60
61config ROCKCHIP_RK3288
62	bool "Support Rockchip RK3288"
63	select CPU_V7A
64	select SPL_BOARD_INIT if SPL
65	select SUPPORT_SPL
66	select SPL
67	imply USB_FUNCTION_ROCKUSB
68	imply CMD_ROCKUSB
69	help
70	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
71	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
72	  video interfaces supporting HDMI and eDP, several DDR3 options
73	  and video codec support. Peripherals include Gigabit Ethernet,
74	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
75
76if ROCKCHIP_RK3288
77
78config TPL_LDSCRIPT
79	default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
80
81config TPL_TEXT_BASE
82	default 0xff704000
83
84config TPL_MAX_SIZE
85	default 32768
86
87endif
88
89config ROCKCHIP_RK3328
90	bool "Support Rockchip RK3328"
91	select ARM64
92	help
93	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
94	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
95	  video interfaces supporting HDMI and eDP, several DDR3 options
96	  and video codec support. Peripherals include Gigabit Ethernet,
97	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
98
99config ROCKCHIP_RK3368
100	bool "Support Rockchip RK3368"
101	select ARM64
102	select SUPPORT_SPL
103	select SUPPORT_TPL
104	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
105	select TPL_NEEDS_SEPARATE_STACK if TPL
106	imply SPL_SEPARATE_BSS
107	imply SPL_SERIAL_SUPPORT
108	imply TPL_SERIAL_SUPPORT
109	select DEBUG_UART_BOARD_INIT
110	help
111	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
112	  into a big and little cluster with 4 cores each) Cortex-A53 including
113	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
114	  (for the little cluster), PowerVR G6110 based graphics, one video
115	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
116	  video codec support.
117
118	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
119	  I2S, UARTs, SPI, I2C and PWMs.
120
121if ROCKCHIP_RK3368
122
123config TPL_LDSCRIPT
124	default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
125
126config TPL_TEXT_BASE
127        default 0xff8c1000
128
129config TPL_MAX_SIZE
130        default 28672
131
132config TPL_STACK
133        default 0xff8cffff
134
135endif
136
137config ROCKCHIP_RK3399
138	bool "Support Rockchip RK3399"
139	select ARM64
140	select SUPPORT_SPL
141	select SPL
142	select SPL_SEPARATE_BSS
143	select SPL_SERIAL_SUPPORT
144	select SPL_DRIVERS_MISC_SUPPORT
145	select DEBUG_UART_BOARD_INIT
146	select BOARD_LATE_INIT
147	select ROCKCHIP_BROM_HELPER
148	help
149	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
150	  and quad-core Cortex-A53.
151	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
152	  video interfaces supporting HDMI and eDP, several DDR3 options
153	  and video codec support. Peripherals include Gigabit Ethernet,
154	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
155
156config ROCKCHIP_RV1108
157	bool "Support Rockchip RV1108"
158	select CPU_V7A
159	help
160	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
161	  and a DSP.
162
163config ROCKCHIP_USB_UART
164	bool "Route uart output to usb pins"
165	help
166	  Rockchip SoCs have the ability to route the signals of the debug
167	  uart through the d+ and d- pins of a specific usb phy to enable
168	  some form of closed-case debugging. With this option supported
169	  SoCs will enable this routing as a debug measure.
170
171config SPL_ROCKCHIP_BACK_TO_BROM
172	bool "SPL returns to bootrom"
173	default y if ROCKCHIP_RK3036
174	select ROCKCHIP_BROM_HELPER
175	depends on SPL
176	help
177	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
178          SPL will return to the boot rom, which will then load the U-Boot
179          binary to keep going on.
180
181config TPL_ROCKCHIP_BACK_TO_BROM
182	bool "TPL returns to bootrom"
183	default y if ROCKCHIP_RK3368
184	select ROCKCHIP_BROM_HELPER
185	depends on TPL
186	help
187	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
188          SPL will return to the boot rom, which will then load the U-Boot
189          binary to keep going on.
190
191config ROCKCHIP_BOOT_MODE_REG
192	hex "Rockchip boot mode flag register address"
193	default 0x200081c8 if ROCKCHIP_RK3036
194	default 0x20004040 if ROCKCHIP_RK3188
195	default 0x110005c8 if ROCKCHIP_RK322X
196	default 0xff730094 if ROCKCHIP_RK3288
197	default 0xff738200 if ROCKCHIP_RK3368
198	default 0xff320300 if ROCKCHIP_RK3399
199	default 0x10300580 if ROCKCHIP_RV1108
200	default 0
201	help
202	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
203	  according to the value from this register.
204
205config ROCKCHIP_SPL_RESERVE_IRAM
206	hex "Size of IRAM reserved in SPL"
207	default 0
208	help
209	  SPL may need reserve memory for firmware loaded by SPL, whose load
210	  address is in IRAM and may overlay with SPL text area if not
211	  reserved.
212
213config ROCKCHIP_BROM_HELPER
214	bool
215
216config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
217        bool "SPL requires early-return (for RK3188-style BROM) to BROM"
218	depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
219	help
220	  Some Rockchip BROM variants (e.g. on the RK3188) load the
221	  first stage in segments and enter multiple times. E.g. on
222	  the RK3188, the first 1KB of the first stage are loaded
223	  first and entered; after returning to the BROM, the
224	  remainder of the first stage is loaded, but the BROM
225	  re-enters at the same address/to the same code as previously.
226
227	  This enables support code in the BOOT0 hook for the SPL stage
228	  to allow multiple entries.
229
230config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
231        bool "TPL requires early-return (for RK3188-style BROM) to BROM"
232	depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
233	help
234	  Some Rockchip BROM variants (e.g. on the RK3188) load the
235	  first stage in segments and enter multiple times. E.g. on
236	  the RK3188, the first 1KB of the first stage are loaded
237	  first and entered; after returning to the BROM, the
238	  remainder of the first stage is loaded, but the BROM
239	  re-enters at the same address/to the same code as previously.
240
241	  This enables support code in the BOOT0 hook for the TPL stage
242	  to allow multiple entries.
243
244config SPL_MMC_SUPPORT
245	default y if !SPL_ROCKCHIP_BACK_TO_BROM
246
247source "arch/arm/mach-rockchip/rk3036/Kconfig"
248source "arch/arm/mach-rockchip/rk3128/Kconfig"
249source "arch/arm/mach-rockchip/rk3188/Kconfig"
250source "arch/arm/mach-rockchip/rk322x/Kconfig"
251source "arch/arm/mach-rockchip/rk3288/Kconfig"
252source "arch/arm/mach-rockchip/rk3328/Kconfig"
253source "arch/arm/mach-rockchip/rk3368/Kconfig"
254source "arch/arm/mach-rockchip/rk3399/Kconfig"
255source "arch/arm/mach-rockchip/rv1108/Kconfig"
256endif
257