1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * Common board functions for AM33XX based boards 6 * 7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <debug_uart.h> 13 #include <errno.h> 14 #include <ns16550.h> 15 #include <spl.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/i2c.h> 23 #include <asm/arch/mem.h> 24 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <asm/omap_common.h> 30 #include <i2c.h> 31 #include <miiphy.h> 32 #include <cpsw.h> 33 #include <linux/errno.h> 34 #include <linux/compiler.h> 35 #include <linux/usb/ch9.h> 36 #include <linux/usb/gadget.h> 37 #include <linux/usb/musb.h> 38 #include <asm/omap_musb.h> 39 #include <asm/davinci_rtc.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 int dram_init(void) 44 { 45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 46 sdram_init(); 47 #endif 48 49 /* dram_init must store complete ramsize in gd->ram_size */ 50 gd->ram_size = get_ram_size( 51 (void *)CONFIG_SYS_SDRAM_BASE, 52 CONFIG_MAX_RAM_BANK_SIZE); 53 return 0; 54 } 55 56 int dram_init_banksize(void) 57 { 58 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 59 gd->bd->bi_dram[0].size = gd->ram_size; 60 61 return 0; 62 } 63 64 #if !CONFIG_IS_ENABLED(OF_CONTROL) 65 static const struct ns16550_platdata am33xx_serial[] = { 66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, 67 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 68 # ifdef CONFIG_SYS_NS16550_COM2 69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, 70 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 71 # ifdef CONFIG_SYS_NS16550_COM3 72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, 73 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, 75 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, 77 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, 79 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, 80 # endif 81 # endif 82 }; 83 84 U_BOOT_DEVICES(am33xx_uarts) = { 85 { "ns16550_serial", &am33xx_serial[0] }, 86 # ifdef CONFIG_SYS_NS16550_COM2 87 { "ns16550_serial", &am33xx_serial[1] }, 88 # ifdef CONFIG_SYS_NS16550_COM3 89 { "ns16550_serial", &am33xx_serial[2] }, 90 { "ns16550_serial", &am33xx_serial[3] }, 91 { "ns16550_serial", &am33xx_serial[4] }, 92 { "ns16550_serial", &am33xx_serial[5] }, 93 # endif 94 # endif 95 }; 96 97 #ifdef CONFIG_DM_I2C 98 static const struct omap_i2c_platdata am33xx_i2c[] = { 99 { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, 100 { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, 101 { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, 102 }; 103 104 U_BOOT_DEVICES(am33xx_i2c) = { 105 { "i2c_omap", &am33xx_i2c[0] }, 106 { "i2c_omap", &am33xx_i2c[1] }, 107 { "i2c_omap", &am33xx_i2c[2] }, 108 }; 109 #endif 110 111 #ifdef CONFIG_DM_GPIO 112 static const struct omap_gpio_platdata am33xx_gpio[] = { 113 { 0, AM33XX_GPIO0_BASE }, 114 { 1, AM33XX_GPIO1_BASE }, 115 { 2, AM33XX_GPIO2_BASE }, 116 { 3, AM33XX_GPIO3_BASE }, 117 #ifdef CONFIG_AM43XX 118 { 4, AM33XX_GPIO4_BASE }, 119 { 5, AM33XX_GPIO5_BASE }, 120 #endif 121 }; 122 123 U_BOOT_DEVICES(am33xx_gpios) = { 124 { "gpio_omap", &am33xx_gpio[0] }, 125 { "gpio_omap", &am33xx_gpio[1] }, 126 { "gpio_omap", &am33xx_gpio[2] }, 127 { "gpio_omap", &am33xx_gpio[3] }, 128 #ifdef CONFIG_AM43XX 129 { "gpio_omap", &am33xx_gpio[4] }, 130 { "gpio_omap", &am33xx_gpio[5] }, 131 #endif 132 }; 133 #endif 134 #endif 135 136 #ifndef CONFIG_DM_GPIO 137 static const struct gpio_bank gpio_bank_am33xx[] = { 138 { (void *)AM33XX_GPIO0_BASE }, 139 { (void *)AM33XX_GPIO1_BASE }, 140 { (void *)AM33XX_GPIO2_BASE }, 141 { (void *)AM33XX_GPIO3_BASE }, 142 #ifdef CONFIG_AM43XX 143 { (void *)AM33XX_GPIO4_BASE }, 144 { (void *)AM33XX_GPIO5_BASE }, 145 #endif 146 }; 147 148 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 149 #endif 150 151 #if defined(CONFIG_MMC_OMAP_HS) 152 int cpu_mmc_init(bd_t *bis) 153 { 154 int ret; 155 156 ret = omap_mmc_init(0, 0, 0, -1, -1); 157 if (ret) 158 return ret; 159 160 return omap_mmc_init(1, 0, 0, -1, -1); 161 } 162 #endif 163 164 /* 165 * RTC only with DDR in self-refresh mode magic value, checked against during 166 * boot to see if we have a valid config. This should be in sync with the value 167 * that will be in drivers/soc/ti/pm33xx.c. 168 */ 169 #define RTC_MAGIC_VAL 0x8cd0 170 171 /* Board type field bit shift for RTC only with DDR in self-refresh mode */ 172 #define RTC_BOARD_TYPE_SHIFT 16 173 174 /* AM33XX has two MUSB controllers which can be host or gadget */ 175 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ 176 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ 177 (!defined(CONFIG_DM_USB)) 178 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 179 180 /* USB 2.0 PHY Control */ 181 #define CM_PHY_PWRDN (1 << 0) 182 #define CM_PHY_OTG_PWRDN (1 << 1) 183 #define OTGVDET_EN (1 << 19) 184 #define OTGSESSENDEN (1 << 20) 185 186 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) 187 { 188 if (on) { 189 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, 190 OTGVDET_EN | OTGSESSENDEN); 191 } else { 192 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); 193 } 194 } 195 196 static struct musb_hdrc_config musb_config = { 197 .multipoint = 1, 198 .dyn_fifo = 1, 199 .num_eps = 16, 200 .ram_bits = 12, 201 }; 202 203 #ifdef CONFIG_AM335X_USB0 204 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) 205 { 206 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); 207 } 208 209 struct omap_musb_board_data otg0_board_data = { 210 .set_phy_power = am33xx_otg0_set_phy_power, 211 }; 212 213 static struct musb_hdrc_platform_data otg0_plat = { 214 .mode = CONFIG_AM335X_USB0_MODE, 215 .config = &musb_config, 216 .power = 50, 217 .platform_ops = &musb_dsps_ops, 218 .board_data = &otg0_board_data, 219 }; 220 #endif 221 222 #ifdef CONFIG_AM335X_USB1 223 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on) 224 { 225 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); 226 } 227 228 struct omap_musb_board_data otg1_board_data = { 229 .set_phy_power = am33xx_otg1_set_phy_power, 230 }; 231 232 static struct musb_hdrc_platform_data otg1_plat = { 233 .mode = CONFIG_AM335X_USB1_MODE, 234 .config = &musb_config, 235 .power = 50, 236 .platform_ops = &musb_dsps_ops, 237 .board_data = &otg1_board_data, 238 }; 239 #endif 240 241 int arch_misc_init(void) 242 { 243 #ifdef CONFIG_AM335X_USB0 244 musb_register(&otg0_plat, &otg0_board_data, 245 (void *)USB0_OTG_BASE); 246 #endif 247 #ifdef CONFIG_AM335X_USB1 248 musb_register(&otg1_plat, &otg1_board_data, 249 (void *)USB1_OTG_BASE); 250 #endif 251 return 0; 252 } 253 254 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 255 256 int arch_misc_init(void) 257 { 258 struct udevice *dev; 259 int ret; 260 261 ret = uclass_first_device(UCLASS_MISC, &dev); 262 if (ret || !dev) 263 return ret; 264 265 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) 266 ret = usb_ether_init(); 267 if (ret) { 268 pr_err("USB ether init failed\n"); 269 return ret; 270 } 271 #endif 272 273 return 0; 274 } 275 276 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ 277 278 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 279 280 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ 281 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) 282 static void rtc32k_unlock(struct davinci_rtc *rtc) 283 { 284 /* 285 * Unlock the RTC's registers. For more details please see the 286 * RTC_SS section of the TRM. In order to unlock we need to 287 * write these specific values (keys) in this order. 288 */ 289 writel(RTC_KICK0R_WE, &rtc->kick0r); 290 writel(RTC_KICK1R_WE, &rtc->kick1r); 291 } 292 #endif 293 294 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 295 /* 296 * Write contents of the RTC_SCRATCH1 register based on board type 297 * Two things are passed 298 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the 299 * control gets to kernel, kernel reads the scratchpad register and gets to 300 * know that bootloader has rtc_only support. 301 * 302 * Second important thing is the board type (16:31). This is needed in the 303 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to 304 * identify the board type and we go ahead and copy the board strings to 305 * am43xx_board_name. 306 */ 307 void update_rtc_magic(void) 308 { 309 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 310 u32 magic = RTC_MAGIC_VAL; 311 312 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT); 313 314 rtc32k_unlock(rtc); 315 316 /* write magic */ 317 writel(magic, &rtc->scratch1); 318 } 319 #endif 320 321 /* 322 * In the case of non-SPL based booting we'll want to call these 323 * functions a tiny bit later as it will require gd to be set and cleared 324 * and that's not true in s_init in this case so we cannot do it there. 325 */ 326 int board_early_init_f(void) 327 { 328 prcm_init(); 329 set_mux_conf_regs(); 330 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 331 update_rtc_magic(); 332 #endif 333 return 0; 334 } 335 336 /* 337 * This function is the place to do per-board things such as ramp up the 338 * MPU clock frequency. 339 */ 340 __weak void am33xx_spl_board_init(void) 341 { 342 } 343 344 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 345 static void rtc32k_enable(void) 346 { 347 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 348 349 rtc32k_unlock(rtc); 350 351 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 352 writel((1 << 3) | (1 << 6), &rtc->osc); 353 } 354 #endif 355 356 static void uart_soft_reset(void) 357 { 358 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 359 u32 regval; 360 361 regval = readl(&uart_base->uartsyscfg); 362 regval |= UART_RESET; 363 writel(regval, &uart_base->uartsyscfg); 364 while ((readl(&uart_base->uartsyssts) & 365 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 366 ; 367 368 /* Disable smart idle */ 369 regval = readl(&uart_base->uartsyscfg); 370 regval |= UART_SMART_IDLE_EN; 371 writel(regval, &uart_base->uartsyscfg); 372 } 373 374 static void watchdog_disable(void) 375 { 376 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 377 378 writel(0xAAAA, &wdtimer->wdtwspr); 379 while (readl(&wdtimer->wdtwwps) != 0x0) 380 ; 381 writel(0x5555, &wdtimer->wdtwspr); 382 while (readl(&wdtimer->wdtwwps) != 0x0) 383 ; 384 } 385 386 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 387 /* 388 * Check if we are executing rtc-only + DDR mode, and resume from it if needed 389 */ 390 static void rtc_only(void) 391 { 392 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; 393 struct prm_device_inst *prm_device = 394 (struct prm_device_inst *)PRM_DEVICE_INST; 395 396 u32 scratch1; 397 void (*resume_func)(void); 398 399 scratch1 = readl(&rtc->scratch1); 400 401 /* 402 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only 403 * written to this register when we want to wake up from RTC only 404 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1: 405 * bits 0-15: RTC_MAGIC_VAL 406 * bits 16-31: board type (needed for sdram_init) 407 */ 408 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL) 409 return; 410 411 rtc32k_unlock(rtc); 412 413 /* Clear RTC magic */ 414 writel(0, &rtc->scratch1); 415 416 /* 417 * Update board type based on value stored on RTC_SCRATCH1, this 418 * is done so that we don't need to read the board type from eeprom 419 * over i2c bus which is expensive 420 */ 421 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT); 422 423 /* 424 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we 425 * are resuming from self-refresh. This avoids an unnecessary re-init 426 * of the DDR. The re-init takes time and we would need to wait for 427 * it to complete before accessing DDR to avoid L3 NOC errors. 428 */ 429 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl); 430 431 rtc_only_prcm_init(); 432 sdram_init(); 433 434 /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ 435 writel(0, &prm_device->emif_ctrl); 436 437 resume_func = (void *)readl(&rtc->scratch0); 438 if (resume_func) 439 resume_func(); 440 } 441 #endif 442 443 void s_init(void) 444 { 445 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) 446 rtc_only(); 447 #endif 448 } 449 450 void early_system_init(void) 451 { 452 /* 453 * The ROM will only have set up sufficient pinmux to allow for the 454 * first 4KiB NOR to be read, we must finish doing what we know of 455 * the NOR mux in this space in order to continue. 456 */ 457 #ifdef CONFIG_NOR_BOOT 458 enable_norboot_pin_mux(); 459 #endif 460 watchdog_disable(); 461 set_uart_mux_conf(); 462 setup_early_clocks(); 463 uart_soft_reset(); 464 #ifdef CONFIG_SPL_BUILD 465 /* 466 * Save the boot parameters passed from romcode. 467 * We cannot delay the saving further than this, 468 * to prevent overwrites. 469 */ 470 save_omap_boot_params(); 471 #endif 472 #ifdef CONFIG_DEBUG_UART_OMAP 473 debug_uart_init(); 474 #endif 475 476 #ifdef CONFIG_SPL_BUILD 477 spl_early_init(); 478 #endif 479 480 #ifdef CONFIG_TI_I2C_BOARD_DETECT 481 do_board_detect(); 482 #endif 483 484 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) 485 /* Enable RTC32K clock */ 486 rtc32k_enable(); 487 #endif 488 } 489 490 #ifdef CONFIG_SPL_BUILD 491 void board_init_f(ulong dummy) 492 { 493 hw_data_init(); 494 early_system_init(); 495 board_early_init_f(); 496 sdram_init(); 497 /* dram_init must store complete ramsize in gd->ram_size */ 498 gd->ram_size = get_ram_size( 499 (void *)CONFIG_SYS_SDRAM_BASE, 500 CONFIG_MAX_RAM_BANK_SIZE); 501 } 502 #endif 503 504 #endif 505 506 int arch_cpu_init_dm(void) 507 { 508 hw_data_init(); 509 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 510 early_system_init(); 511 #endif 512 return 0; 513 } 514