xref: /openbmc/u-boot/arch/arm/mach-mvebu/spl.c (revision 333279af23ac08ebc8d8056c677c98964dd013b6)
183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2350b50eeSStefan Roese /*
3a5f88877SStefan Roese  * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4350b50eeSStefan Roese  */
5350b50eeSStefan Roese 
6350b50eeSStefan Roese #include <common.h>
76451223aSStefan Roese #include <dm.h>
86451223aSStefan Roese #include <debug_uart.h>
96451223aSStefan Roese #include <fdtdec.h>
10350b50eeSStefan Roese #include <spl.h>
11350b50eeSStefan Roese #include <asm/io.h>
12350b50eeSStefan Roese #include <asm/arch/cpu.h>
13350b50eeSStefan Roese #include <asm/arch/soc.h>
14350b50eeSStefan Roese 
get_boot_device(void)15a5f88877SStefan Roese static u32 get_boot_device(void)
16350b50eeSStefan Roese {
17a5f88877SStefan Roese 	u32 val;
18a5f88877SStefan Roese 	u32 boot_device;
19a5f88877SStefan Roese 
20f4db6c97SStefan Roese 	/*
21f4db6c97SStefan Roese 	 * First check, if UART boot-mode is active. This can only
22f4db6c97SStefan Roese 	 * be done, via the bootrom error register. Here the
23f4db6c97SStefan Roese 	 * MSB marks if the UART mode is active.
24f4db6c97SStefan Roese 	 */
25f4db6c97SStefan Roese 	val = readl(CONFIG_BOOTROM_ERR_REG);
26f4db6c97SStefan Roese 	boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
27f4db6c97SStefan Roese 	debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
28f4db6c97SStefan Roese 	if (boot_device == BOOTROM_ERR_MODE_UART)
29f4db6c97SStefan Roese 		return BOOT_DEVICE_UART;
30f4db6c97SStefan Roese 
31*2fd42840SChris Packham #ifdef CONFIG_ARMADA_38X
32*2fd42840SChris Packham 	/*
33*2fd42840SChris Packham 	 * If the bootrom error code contains any other than zeros it's an
34*2fd42840SChris Packham 	 * error condition and the bootROM has fallen back to UART boot
35*2fd42840SChris Packham 	 */
36*2fd42840SChris Packham 	boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
37*2fd42840SChris Packham 	if (boot_device)
38*2fd42840SChris Packham 		return BOOT_DEVICE_UART;
39*2fd42840SChris Packham #endif
40*2fd42840SChris Packham 
41f4db6c97SStefan Roese 	/*
42f4db6c97SStefan Roese 	 * Now check the SAR register for the strapped boot-device
43f4db6c97SStefan Roese 	 */
44a5f88877SStefan Roese 	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */
45a5f88877SStefan Roese 	boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
46f4db6c97SStefan Roese 	debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
47a5f88877SStefan Roese 	switch (boot_device) {
48926c8b2eSSean Nyekjaer #if defined(CONFIG_ARMADA_38X)
49926c8b2eSSean Nyekjaer 	case BOOT_FROM_NAND:
50926c8b2eSSean Nyekjaer 		return BOOT_DEVICE_NAND;
51926c8b2eSSean Nyekjaer #endif
52a5f88877SStefan Roese #ifdef CONFIG_SPL_MMC_SUPPORT
53a5f88877SStefan Roese 	case BOOT_FROM_MMC:
54a5f88877SStefan Roese 	case BOOT_FROM_MMC_ALT:
558ed43b96SStefan Roese 		return BOOT_DEVICE_MMC1;
568ed43b96SStefan Roese #endif
57a5f88877SStefan Roese 	case BOOT_FROM_UART:
58f3a88e2cSBaruch Siach #ifdef BOOT_FROM_UART_ALT
59f3a88e2cSBaruch Siach 	case BOOT_FROM_UART_ALT:
60f3a88e2cSBaruch Siach #endif
61a5f88877SStefan Roese 		return BOOT_DEVICE_UART;
62a5f88877SStefan Roese 	case BOOT_FROM_SPI:
63a5f88877SStefan Roese 	default:
64a5f88877SStefan Roese 		return BOOT_DEVICE_SPI;
65a5f88877SStefan Roese 	};
66a5f88877SStefan Roese }
67a5f88877SStefan Roese 
spl_boot_device(void)68a5f88877SStefan Roese u32 spl_boot_device(void)
69a5f88877SStefan Roese {
70a5f88877SStefan Roese 	return get_boot_device();
71350b50eeSStefan Roese }
72350b50eeSStefan Roese 
board_init_f(ulong dummy)73350b50eeSStefan Roese void board_init_f(ulong dummy)
74350b50eeSStefan Roese {
756451223aSStefan Roese 	int ret;
766451223aSStefan Roese 
77e3cccf9eSStefan Roese 	/*
78e3cccf9eSStefan Roese 	 * Pin muxing needs to be done before UART output, since
79e3cccf9eSStefan Roese 	 * on A38x the UART pins need some re-muxing for output
80e3cccf9eSStefan Roese 	 * to work.
81e3cccf9eSStefan Roese 	 */
82e3cccf9eSStefan Roese 	board_early_init_f();
83e3cccf9eSStefan Roese 
846451223aSStefan Roese 	/* Example code showing how to enable the debug UART on MVEBU */
856451223aSStefan Roese #ifdef EARLY_UART
866451223aSStefan Roese 	/*
876451223aSStefan Roese 	 * Debug UART can be used from here if required:
886451223aSStefan Roese 	 *
896451223aSStefan Roese 	 * debug_uart_init();
906451223aSStefan Roese 	 * printch('a');
916451223aSStefan Roese 	 * printhex8(0x1234);
926451223aSStefan Roese 	 * printascii("string");
936451223aSStefan Roese 	 */
946451223aSStefan Roese #endif
956451223aSStefan Roese 
966451223aSStefan Roese 	ret = spl_init();
976451223aSStefan Roese 	if (ret) {
986451223aSStefan Roese 		debug("spl_init() failed: %d\n", ret);
996451223aSStefan Roese 		hang();
1006451223aSStefan Roese 	}
1016451223aSStefan Roese 
1026451223aSStefan Roese 	/* Use special translation offset for SPL */
1036451223aSStefan Roese 	dm_set_translation_offset(0xd0000000 - 0xf1000000);
1046451223aSStefan Roese 
105350b50eeSStefan Roese 	preloader_console_init();
106350b50eeSStefan Roese 
107ade741b3SStefan Roese 	timer_init();
108ade741b3SStefan Roese 
10909e89ab4SStefan Roese 	/* Armada 375 does not support SerDes and DDR3 init yet */
11009e89ab4SStefan Roese #if !defined(CONFIG_ARMADA_375)
111350b50eeSStefan Roese 	/* First init the serdes PHY's */
112350b50eeSStefan Roese 	serdes_phy_config();
113350b50eeSStefan Roese 
114350b50eeSStefan Roese 	/* Setup DDR */
115350b50eeSStefan Roese 	ddr3_init();
11609e89ab4SStefan Roese #endif
117350b50eeSStefan Roese 
118944c7a31SStefan Roese 	/*
119944c7a31SStefan Roese 	 * Return to the BootROM to continue the Marvell xmodem
120944c7a31SStefan Roese 	 * UART boot protocol. As initiated by the kwboot tool.
121944c7a31SStefan Roese 	 *
122944c7a31SStefan Roese 	 * This can only be done by the BootROM and not by the
123944c7a31SStefan Roese 	 * U-Boot SPL infrastructure, since the beginning of the
124944c7a31SStefan Roese 	 * image is already read and interpreted by the BootROM.
125944c7a31SStefan Roese 	 * SPL has no chance to receive this information. So we
126944c7a31SStefan Roese 	 * need to return to the BootROM to enable this xmodem
127944c7a31SStefan Roese 	 * UART download.
128926c8b2eSSean Nyekjaer 	 *
129926c8b2eSSean Nyekjaer 	 * If booting from NAND lets let the BootROM load the
130926c8b2eSSean Nyekjaer 	 * rest of the bootloader.
131944c7a31SStefan Roese 	 */
132926c8b2eSSean Nyekjaer 	switch (get_boot_device()) {
133926c8b2eSSean Nyekjaer 		case BOOT_DEVICE_UART:
134926c8b2eSSean Nyekjaer #if defined(CONFIG_ARMADA_38X)
135926c8b2eSSean Nyekjaer 		case BOOT_DEVICE_NAND:
136926c8b2eSSean Nyekjaer #endif
137944c7a31SStefan Roese 			return_to_bootrom();
138350b50eeSStefan Roese 	}
139926c8b2eSSean Nyekjaer }
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