183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 28cb78722SStefan Roese /* 38cb78722SStefan Roese * (C) Copyright 2009 48cb78722SStefan Roese * Marvell Semiconductor <www.marvell.com> 58cb78722SStefan Roese * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 68cb78722SStefan Roese */ 78cb78722SStefan Roese 8250eea74SStefan Roese #ifndef _MVEBU_CPU_H 9250eea74SStefan Roese #define _MVEBU_CPU_H 108cb78722SStefan Roese 118cb78722SStefan Roese #include <asm/system.h> 128cb78722SStefan Roese 138cb78722SStefan Roese #ifndef __ASSEMBLY__ 148cb78722SStefan Roese 158cb78722SStefan Roese #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) 168cb78722SStefan Roese #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) 178cb78722SStefan Roese 188cb78722SStefan Roese enum memory_bank { 198cb78722SStefan Roese BANK0, 208cb78722SStefan Roese BANK1, 218cb78722SStefan Roese BANK2, 228cb78722SStefan Roese BANK3 238cb78722SStefan Roese }; 248cb78722SStefan Roese 258cb78722SStefan Roese enum cpu_winen { 268cb78722SStefan Roese CPU_WIN_DISABLE, 278cb78722SStefan Roese CPU_WIN_ENABLE 288cb78722SStefan Roese }; 298cb78722SStefan Roese 308cb78722SStefan Roese enum cpu_target { 318cb78722SStefan Roese CPU_TARGET_DRAM = 0x0, 328cb78722SStefan Roese CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, 338cb78722SStefan Roese CPU_TARGET_ETH23 = 0x3, 348cb78722SStefan Roese CPU_TARGET_PCIE02 = 0x4, 358cb78722SStefan Roese CPU_TARGET_ETH01 = 0x7, 368cb78722SStefan Roese CPU_TARGET_PCIE13 = 0x8, 378cb78722SStefan Roese CPU_TARGET_SASRAM = 0x9, 38a1b6b0a9SMario Six CPU_TARGET_SATA01 = 0xa, /* A38X */ 398cb78722SStefan Roese CPU_TARGET_NAND = 0xd, 40a1b6b0a9SMario Six CPU_TARGET_SATA23_DFX = 0xe, /* A38X */ 418cb78722SStefan Roese }; 428cb78722SStefan Roese 438cb78722SStefan Roese enum cpu_attrib { 448cb78722SStefan Roese CPU_ATTR_SASRAM = 0x01, 458cb78722SStefan Roese CPU_ATTR_DRAM_CS0 = 0x0e, 468cb78722SStefan Roese CPU_ATTR_DRAM_CS1 = 0x0d, 478cb78722SStefan Roese CPU_ATTR_DRAM_CS2 = 0x0b, 488cb78722SStefan Roese CPU_ATTR_DRAM_CS3 = 0x07, 498cb78722SStefan Roese CPU_ATTR_NANDFLASH = 0x2f, 508cb78722SStefan Roese CPU_ATTR_SPIFLASH = 0x1e, 5121324ddbSStefan Roese CPU_ATTR_SPI0_CS0 = 0x1e, 5221324ddbSStefan Roese CPU_ATTR_SPI0_CS1 = 0x5e, 5321324ddbSStefan Roese CPU_ATTR_SPI1_CS2 = 0x9a, 548cb78722SStefan Roese CPU_ATTR_BOOTROM = 0x1d, 558cb78722SStefan Roese CPU_ATTR_PCIE_IO = 0xe0, 568cb78722SStefan Roese CPU_ATTR_PCIE_MEM = 0xe8, 578cb78722SStefan Roese CPU_ATTR_DEV_CS0 = 0x3e, 588cb78722SStefan Roese CPU_ATTR_DEV_CS1 = 0x3d, 598cb78722SStefan Roese CPU_ATTR_DEV_CS2 = 0x3b, 608cb78722SStefan Roese CPU_ATTR_DEV_CS3 = 0x37, 618cb78722SStefan Roese }; 628cb78722SStefan Roese 639c6d3b7bSStefan Roese enum { 649c6d3b7bSStefan Roese MVEBU_SOC_AXP, 6509e89ab4SStefan Roese MVEBU_SOC_A375, 669c6d3b7bSStefan Roese MVEBU_SOC_A38X, 670f8031a3SChris Packham MVEBU_SOC_MSYS, 689c6d3b7bSStefan Roese MVEBU_SOC_UNKNOWN, 699c6d3b7bSStefan Roese }; 709c6d3b7bSStefan Roese 71*a8483505SStefan Roese #define MVEBU_SDRAM_SIZE_MAX 0xc0000000 72*a8483505SStefan Roese 738cb78722SStefan Roese /* 748cb78722SStefan Roese * Default Device Address MAP BAR values 758cb78722SStefan Roese */ 76*a8483505SStefan Roese #define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX 778ed20d65SStefan Roese #define MBUS_PCI_MEM_SIZE (128 << 20) 788ed20d65SStefan Roese #define MBUS_PCI_IO_BASE 0xF1100000 798ed20d65SStefan Roese #define MBUS_PCI_IO_SIZE (64 << 10) 808ed20d65SStefan Roese #define MBUS_SPI_BASE 0xF4000000 818ed20d65SStefan Roese #define MBUS_SPI_SIZE (8 << 20) 828ed20d65SStefan Roese #define MBUS_BOOTROM_BASE 0xF8000000 838ed20d65SStefan Roese #define MBUS_BOOTROM_SIZE (8 << 20) 848cb78722SStefan Roese 858cb78722SStefan Roese struct mbus_win { 868cb78722SStefan Roese u32 base; 878cb78722SStefan Roese u32 size; 888cb78722SStefan Roese u8 target; 898cb78722SStefan Roese u8 attr; 908cb78722SStefan Roese }; 918cb78722SStefan Roese 928cb78722SStefan Roese /* 938cb78722SStefan Roese * System registers 948cb78722SStefan Roese * Ref: Datasheet sec:A.28 958cb78722SStefan Roese */ 968cb78722SStefan Roese struct mvebu_system_registers { 9709e89ab4SStefan Roese #if defined(CONFIG_ARMADA_375) 9809e89ab4SStefan Roese u8 pad1[0x54]; 9909e89ab4SStefan Roese #else 1008cb78722SStefan Roese u8 pad1[0x60]; 10109e89ab4SStefan Roese #endif 1028cb78722SStefan Roese u32 rstoutn_mask; /* 0x60 */ 1038cb78722SStefan Roese u32 sys_soft_rst; /* 0x64 */ 1048cb78722SStefan Roese }; 1058cb78722SStefan Roese 1068cb78722SStefan Roese /* 1078cb78722SStefan Roese * GPIO Registers 1088cb78722SStefan Roese * Ref: Datasheet sec:A.19 1098cb78722SStefan Roese */ 1108cb78722SStefan Roese struct kwgpio_registers { 1118cb78722SStefan Roese u32 dout; 1128cb78722SStefan Roese u32 oe; 1138cb78722SStefan Roese u32 blink_en; 1148cb78722SStefan Roese u32 din_pol; 1158cb78722SStefan Roese u32 din; 1168cb78722SStefan Roese u32 irq_cause; 1178cb78722SStefan Roese u32 irq_mask; 1188cb78722SStefan Roese u32 irq_level; 1198cb78722SStefan Roese }; 1208cb78722SStefan Roese 121d718bf2cSStefan Roese struct sar_freq_modes { 122d718bf2cSStefan Roese u8 val; 123d718bf2cSStefan Roese u8 ffc; /* Fabric Frequency Configuration */ 124d718bf2cSStefan Roese u32 p_clk; 125d718bf2cSStefan Roese u32 nb_clk; 126d718bf2cSStefan Roese u32 d_clk; 127d718bf2cSStefan Roese }; 128d718bf2cSStefan Roese 1298cb78722SStefan Roese /* Needed for dynamic (board-specific) mbus configuration */ 1308cb78722SStefan Roese extern struct mvebu_mbus_state mbus_state; 1318cb78722SStefan Roese 1328cb78722SStefan Roese /* 1338cb78722SStefan Roese * functions 1348cb78722SStefan Roese */ 1358cb78722SStefan Roese unsigned int mvebu_sdram_bar(enum memory_bank bank); 1368cb78722SStefan Roese unsigned int mvebu_sdram_bs(enum memory_bank bank); 1378cb78722SStefan Roese void mvebu_sdram_size_adjust(enum memory_bank bank); 1388cb78722SStefan Roese int mvebu_mbus_probe(struct mbus_win windows[], int count); 1399c6d3b7bSStefan Roese int mvebu_soc_family(void); 1402a0b7dc3SStefan Roese u32 mvebu_get_nand_clock(void); 1418cb78722SStefan Roese 142944c7a31SStefan Roese void return_to_bootrom(void); 143944c7a31SStefan Roese 1447f1adcd7SStefan Roese int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); 1457f1adcd7SStefan Roese 146d718bf2cSStefan Roese void get_sar_freq(struct sar_freq_modes *sar_freq); 147d718bf2cSStefan Roese 1488cb78722SStefan Roese /* 1498cb78722SStefan Roese * Highspeed SERDES PHY config init, ported from bin_hdr 1508cb78722SStefan Roese * to mainline U-Boot 1518cb78722SStefan Roese */ 1528cb78722SStefan Roese int serdes_phy_config(void); 1538cb78722SStefan Roese 1548cb78722SStefan Roese /* 1558cb78722SStefan Roese * DDR3 init / training code ported from Marvell bin_hdr. Now 1568cb78722SStefan Roese * available in mainline U-Boot in: 157ff9112dfSStefan Roese * drivers/ddr/marvell 1588cb78722SStefan Roese */ 1598cb78722SStefan Roese int ddr3_init(void); 160913d1be2SStefan Roese 161f61aefc1SStefan Roese /* 162f61aefc1SStefan Roese * get_ref_clk 163f61aefc1SStefan Roese * 164f61aefc1SStefan Roese * return: reference clock in MHz (25 or 40) 165f61aefc1SStefan Roese */ 166f61aefc1SStefan Roese u32 get_ref_clk(void); 167f61aefc1SStefan Roese 1688cb78722SStefan Roese #endif /* __ASSEMBLY__ */ 169250eea74SStefan Roese #endif /* _MVEBU_CPU_H */ 170