1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ahci.h> 9 #include <linux/mbus.h> 10 #include <asm/io.h> 11 #include <asm/pl310.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/soc.h> 14 #include <sdhci.h> 15 16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 18 19 static struct mbus_win windows[] = { 20 /* SPI */ 21 { MBUS_SPI_BASE, MBUS_SPI_SIZE, 22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, 23 24 /* NOR */ 25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, 26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, 27 }; 28 29 void lowlevel_init(void) 30 { 31 /* 32 * Dummy implementation, we only need LOWLEVEL_INIT 33 * on Armada to configure CP15 in start.S / cpu_init_cp15() 34 */ 35 } 36 37 void reset_cpu(unsigned long ignored) 38 { 39 struct mvebu_system_registers *reg = 40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 41 42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 44 while (1) 45 ; 46 } 47 48 int mvebu_soc_family(void) 49 { 50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 51 52 if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID)) 53 return MVEBU_SOC_AXP; 54 55 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || 56 devid == SOC_88F6828_ID) 57 return MVEBU_SOC_A38X; 58 59 return MVEBU_SOC_UNKNOWN; 60 } 61 62 #if defined(CONFIG_DISPLAY_CPUINFO) 63 64 #if defined(CONFIG_ARMADA_38X) 65 /* SAR values for Armada 38x */ 66 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) 67 #define SAR_CPU_FREQ_OFFS 10 68 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) 69 70 struct sar_freq_modes sar_freq_tab[] = { 71 { 0x0, 0x0, 666, 333, 333 }, 72 { 0x2, 0x0, 800, 400, 400 }, 73 { 0x4, 0x0, 1066, 533, 533 }, 74 { 0x6, 0x0, 1200, 600, 600 }, 75 { 0x8, 0x0, 1332, 666, 666 }, 76 { 0xc, 0x0, 1600, 800, 800 }, 77 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 78 }; 79 #else 80 /* SAR values for Armada XP */ 81 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) 82 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) 83 #define SAR_CPU_FREQ_OFFS 21 84 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) 85 #define SAR_FFC_FREQ_OFFS 24 86 #define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) 87 #define SAR2_CPU_FREQ_OFFS 20 88 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) 89 90 struct sar_freq_modes sar_freq_tab[] = { 91 { 0xa, 0x5, 800, 400, 400 }, 92 { 0x1, 0x5, 1066, 533, 533 }, 93 { 0x2, 0x5, 1200, 600, 600 }, 94 { 0x2, 0x9, 1200, 600, 400 }, 95 { 0x3, 0x5, 1333, 667, 667 }, 96 { 0x4, 0x5, 1500, 750, 750 }, 97 { 0x4, 0x9, 1500, 750, 500 }, 98 { 0xb, 0x9, 1600, 800, 533 }, 99 { 0xb, 0xa, 1600, 800, 640 }, 100 { 0xb, 0x5, 1600, 800, 800 }, 101 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ 102 }; 103 #endif 104 105 void get_sar_freq(struct sar_freq_modes *sar_freq) 106 { 107 u32 val; 108 u32 freq; 109 int i; 110 111 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ 112 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; 113 #if !defined(CONFIG_ARMADA_38X) 114 /* 115 * Shift CPU0 clock frequency select bit from SAR2 register 116 * into correct position 117 */ 118 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) 119 >> SAR2_CPU_FREQ_OFFS) << 3; 120 #endif 121 for (i = 0; sar_freq_tab[i].val != 0xff; i++) { 122 if (sar_freq_tab[i].val == freq) { 123 #if defined(CONFIG_ARMADA_38X) 124 *sar_freq = sar_freq_tab[i]; 125 return; 126 #else 127 int k; 128 u8 ffc; 129 130 ffc = (val & SAR_FFC_FREQ_MASK) >> 131 SAR_FFC_FREQ_OFFS; 132 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { 133 if (sar_freq_tab[k].ffc == ffc) { 134 *sar_freq = sar_freq_tab[k]; 135 return; 136 } 137 } 138 i = k; 139 #endif 140 } 141 } 142 143 /* SAR value not found, return 0 for frequencies */ 144 *sar_freq = sar_freq_tab[i - 1]; 145 } 146 147 int print_cpuinfo(void) 148 { 149 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 150 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 151 struct sar_freq_modes sar_freq; 152 153 puts("SoC: "); 154 155 switch (devid) { 156 case SOC_MV78260_ID: 157 puts("MV78260-"); 158 break; 159 case SOC_MV78460_ID: 160 puts("MV78460-"); 161 break; 162 case SOC_88F6810_ID: 163 puts("MV88F6810-"); 164 break; 165 case SOC_88F6820_ID: 166 puts("MV88F6820-"); 167 break; 168 case SOC_88F6828_ID: 169 puts("MV88F6828-"); 170 break; 171 default: 172 puts("Unknown-"); 173 break; 174 } 175 176 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 177 switch (revid) { 178 case 1: 179 puts("A0"); 180 break; 181 case 2: 182 puts("B0"); 183 break; 184 default: 185 printf("?? (%x)", revid); 186 break; 187 } 188 } 189 190 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 191 switch (revid) { 192 case MV_88F68XX_Z1_ID: 193 puts("Z1"); 194 break; 195 case MV_88F68XX_A0_ID: 196 puts("A0"); 197 break; 198 default: 199 printf("?? (%x)", revid); 200 break; 201 } 202 } 203 204 get_sar_freq(&sar_freq); 205 printf(" at %d MHz\n", sar_freq.p_clk); 206 207 return 0; 208 } 209 #endif /* CONFIG_DISPLAY_CPUINFO */ 210 211 /* 212 * This function initialize Controller DRAM Fastpath windows. 213 * It takes the CS size information from the 0x1500 scratch registers 214 * and sets the correct windows sizes and base addresses accordingly. 215 * 216 * These values are set in the scratch registers by the Marvell 217 * DDR3 training code, which is executed by the BootROM before the 218 * main payload (U-Boot) is executed. This training code is currently 219 * only available in the Marvell U-Boot version. It needs to be 220 * ported to mainline U-Boot SPL at some point. 221 */ 222 static void update_sdram_window_sizes(void) 223 { 224 u64 base = 0; 225 u32 size, temp; 226 int i; 227 228 for (i = 0; i < SDRAM_MAX_CS; i++) { 229 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 230 if (size != 0) { 231 size |= ~(SDRAM_ADDR_MASK); 232 233 /* Set Base Address */ 234 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 235 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 236 237 /* 238 * Check if out of max window size and resize 239 * the window 240 */ 241 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 242 ~(SDRAM_ADDR_MASK)) | 1; 243 temp |= (size & SDRAM_ADDR_MASK); 244 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 245 246 base += ((u64)size + 1); 247 } else { 248 /* 249 * Disable window if not used, otherwise this 250 * leads to overlapping enabled windows with 251 * pretty strange results 252 */ 253 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 254 } 255 } 256 } 257 258 void mmu_disable(void) 259 { 260 asm volatile( 261 "mrc p15, 0, r0, c1, c0, 0\n" 262 "bic r0, #1\n" 263 "mcr p15, 0, r0, c1, c0, 0\n"); 264 } 265 266 #ifdef CONFIG_ARCH_CPU_INIT 267 static void set_cbar(u32 addr) 268 { 269 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); 270 } 271 272 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) 273 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2)) 274 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \ 275 (((addr) & 0xF) << 6)) 276 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ 277 (((reg) & 0xF) << 2)) 278 279 static void setup_usb_phys(void) 280 { 281 int dev; 282 283 /* 284 * USB PLL init 285 */ 286 287 /* Setup PLL frequency */ 288 /* USB REF frequency = 25 MHz */ 289 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605); 290 291 /* Power up PLL and PHY channel */ 292 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9)); 293 294 /* Assert VCOCAL_START */ 295 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21)); 296 297 mdelay(1); 298 299 /* 300 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60) 301 */ 302 303 for (dev = 0; dev < 3; dev++) { 304 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15)); 305 306 /* Assert REG_RCAL_START in channel REG 1 */ 307 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 308 udelay(40); 309 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); 310 } 311 } 312 313 /* 314 * This function is not called from the SPL U-Boot version 315 */ 316 int arch_cpu_init(void) 317 { 318 struct pl310_regs *const pl310 = 319 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 320 321 /* 322 * Only with disabled MMU its possible to switch the base 323 * register address on Armada 38x. Without this the SDRAM 324 * located at >= 0x4000.0000 is also not accessible, as its 325 * still locked to cache. 326 */ 327 mmu_disable(); 328 329 /* Linux expects the internal registers to be at 0xf1000000 */ 330 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 331 set_cbar(SOC_REGS_PHY_BASE + 0xC000); 332 333 /* 334 * From this stage on, the SoC detection is working. As we have 335 * configured the internal register base to the value used 336 * in the macros / defines in the U-Boot header (soc.h). 337 */ 338 339 if (mvebu_soc_family() == MVEBU_SOC_A38X) { 340 /* 341 * To fully release / unlock this area from cache, we need 342 * to flush all caches and disable the L2 cache. 343 */ 344 icache_disable(); 345 dcache_disable(); 346 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 347 } 348 349 /* 350 * We need to call mvebu_mbus_probe() before calling 351 * update_sdram_window_sizes() as it disables all previously 352 * configured mbus windows and then configures them as 353 * required for U-Boot. Calling update_sdram_window_sizes() 354 * without this configuration will not work, as the internal 355 * registers can't be accessed reliably because of potenial 356 * double mapping. 357 * After updating the SDRAM access windows we need to call 358 * mvebu_mbus_probe() again, as this now correctly configures 359 * the SDRAM areas that are later used by the MVEBU drivers 360 * (e.g. USB, NETA). 361 */ 362 363 /* 364 * First disable all windows 365 */ 366 mvebu_mbus_probe(NULL, 0); 367 368 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 369 /* 370 * Now the SDRAM access windows can be reconfigured using 371 * the information in the SDRAM scratch pad registers 372 */ 373 update_sdram_window_sizes(); 374 } 375 376 /* 377 * Finally the mbus windows can be configured with the 378 * updated SDRAM sizes 379 */ 380 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 381 382 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 383 /* Enable GBE0, GBE1, LCD and NFC PUP */ 384 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, 385 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | 386 NAND_PUP_EN | SPI_PUP_EN); 387 388 /* Configure USB PLL and PHYs on AXP */ 389 setup_usb_phys(); 390 } 391 392 /* Enable NAND and NAND arbiter */ 393 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN); 394 395 /* Disable MBUS error propagation */ 396 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0); 397 398 return 0; 399 } 400 #endif /* CONFIG_ARCH_CPU_INIT */ 401 402 u32 mvebu_get_nand_clock(void) 403 { 404 return CONFIG_SYS_MVEBU_PLL_CLOCK / 405 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) & 406 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS); 407 } 408 409 /* 410 * SOC specific misc init 411 */ 412 #if defined(CONFIG_ARCH_MISC_INIT) 413 int arch_misc_init(void) 414 { 415 /* Nothing yet, perhaps we need something here later */ 416 return 0; 417 } 418 #endif /* CONFIG_ARCH_MISC_INIT */ 419 420 #ifdef CONFIG_MV_SDHCI 421 int board_mmc_init(bd_t *bis) 422 { 423 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, 424 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); 425 426 return 0; 427 } 428 #endif 429 430 #ifdef CONFIG_SCSI_AHCI_PLAT 431 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 432 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 433 434 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) 435 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) 436 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) 437 438 static void ahci_mvebu_mbus_config(void __iomem *base) 439 { 440 const struct mbus_dram_target_info *dram; 441 int i; 442 443 dram = mvebu_mbus_dram_info(); 444 445 for (i = 0; i < 4; i++) { 446 writel(0, base + AHCI_WINDOW_CTRL(i)); 447 writel(0, base + AHCI_WINDOW_BASE(i)); 448 writel(0, base + AHCI_WINDOW_SIZE(i)); 449 } 450 451 for (i = 0; i < dram->num_cs; i++) { 452 const struct mbus_dram_window *cs = dram->cs + i; 453 454 writel((cs->mbus_attr << 8) | 455 (dram->mbus_dram_target_id << 4) | 1, 456 base + AHCI_WINDOW_CTRL(i)); 457 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); 458 writel(((cs->size - 1) & 0xffff0000), 459 base + AHCI_WINDOW_SIZE(i)); 460 } 461 } 462 463 static void ahci_mvebu_regret_option(void __iomem *base) 464 { 465 /* 466 * Enable the regret bit to allow the SATA unit to regret a 467 * request that didn't receive an acknowlegde and avoid a 468 * deadlock 469 */ 470 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); 471 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); 472 } 473 474 void scsi_init(void) 475 { 476 printf("MVEBU SATA INIT\n"); 477 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); 478 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); 479 ahci_init((void __iomem *)MVEBU_SATA0_BASE); 480 } 481 #endif 482 483 void enable_caches(void) 484 { 485 /* Avoid problem with e.g. neta ethernet driver */ 486 invalidate_dcache_all(); 487 488 /* Enable D-cache. I-cache is already enabled in start.S */ 489 dcache_enable(); 490 } 491 492 void v7_outer_cache_enable(void) 493 { 494 if (mvebu_soc_family() == MVEBU_SOC_AXP) { 495 struct pl310_regs *const pl310 = 496 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 497 u32 u; 498 499 /* The L2 cache is already disabled at this point */ 500 501 /* 502 * For Aurora cache in no outer mode, enable via the CP15 503 * coprocessor broadcasting of cache commands to L2. 504 */ 505 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 506 u |= BIT(8); /* Set the FW bit */ 507 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 508 509 isb(); 510 511 /* Enable the L2 cache */ 512 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 513 } 514 } 515 516 void v7_outer_cache_disable(void) 517 { 518 struct pl310_regs *const pl310 = 519 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 520 521 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 522 } 523