1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 14 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 15 16 static struct mbus_win windows[] = { 17 /* PCIE MEM address space */ 18 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM }, 19 20 /* PCIE IO address space */ 21 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO }, 22 23 /* SPI */ 24 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 25 CPU_ATTR_SPIFLASH }, 26 27 /* NOR */ 28 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, 29 CPU_ATTR_BOOTROM }, 30 }; 31 32 void reset_cpu(unsigned long ignored) 33 { 34 struct mvebu_system_registers *reg = 35 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; 36 37 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); 38 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); 39 while (1) 40 ; 41 } 42 43 #if defined(CONFIG_DISPLAY_CPUINFO) 44 int print_cpuinfo(void) 45 { 46 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; 47 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; 48 49 puts("SoC: "); 50 51 switch (devid) { 52 case SOC_MV78460_ID: 53 puts("MV78460-"); 54 break; 55 default: 56 puts("Unknown-"); 57 break; 58 } 59 60 switch (revid) { 61 case 1: 62 puts("A0\n"); 63 break; 64 case 2: 65 puts("B0\n"); 66 break; 67 default: 68 puts("??\n"); 69 break; 70 } 71 72 return 0; 73 } 74 #endif /* CONFIG_DISPLAY_CPUINFO */ 75 76 /* 77 * This function initialize Controller DRAM Fastpath windows. 78 * It takes the CS size information from the 0x1500 scratch registers 79 * and sets the correct windows sizes and base addresses accordingly. 80 * 81 * These values are set in the scratch registers by the Marvell 82 * DDR3 training code, which is executed by the BootROM before the 83 * main payload (U-Boot) is executed. This training code is currently 84 * only available in the Marvell U-Boot version. It needs to be 85 * ported to mainline U-Boot SPL at some point. 86 */ 87 static void update_sdram_window_sizes(void) 88 { 89 u64 base = 0; 90 u32 size, temp; 91 int i; 92 93 for (i = 0; i < SDRAM_MAX_CS; i++) { 94 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK; 95 if (size != 0) { 96 size |= ~(SDRAM_ADDR_MASK); 97 98 /* Set Base Address */ 99 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF); 100 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); 101 102 /* 103 * Check if out of max window size and resize 104 * the window 105 */ 106 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) & 107 ~(SDRAM_ADDR_MASK)) | 1; 108 temp |= (size & SDRAM_ADDR_MASK); 109 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)); 110 111 base += ((u64)size + 1); 112 } else { 113 /* 114 * Disable window if not used, otherwise this 115 * leads to overlapping enabled windows with 116 * pretty strange results 117 */ 118 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1); 119 } 120 } 121 } 122 123 #ifdef CONFIG_ARCH_CPU_INIT 124 int arch_cpu_init(void) 125 { 126 /* Linux expects the internal registers to be at 0xf1000000 */ 127 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); 128 129 /* 130 * We need to call mvebu_mbus_probe() before calling 131 * update_sdram_window_sizes() as it disables all previously 132 * configured mbus windows and then configures them as 133 * required for U-Boot. Calling update_sdram_window_sizes() 134 * without this configuration will not work, as the internal 135 * registers can't be accessed reliably because of potenial 136 * double mapping. 137 * After updating the SDRAM access windows we need to call 138 * mvebu_mbus_probe() again, as this now correctly configures 139 * the SDRAM areas that are later used by the MVEBU drivers 140 * (e.g. USB, NETA). 141 */ 142 143 /* 144 * First disable all windows 145 */ 146 mvebu_mbus_probe(NULL, 0); 147 148 /* 149 * Now the SDRAM access windows can be reconfigured using 150 * the information in the SDRAM scratch pad registers 151 */ 152 update_sdram_window_sizes(); 153 154 /* 155 * Finally the mbus windows can be configured with the 156 * updated SDRAM sizes 157 */ 158 mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); 159 160 return 0; 161 } 162 #endif /* CONFIG_ARCH_CPU_INIT */ 163 164 /* 165 * SOC specific misc init 166 */ 167 #if defined(CONFIG_ARCH_MISC_INIT) 168 int arch_misc_init(void) 169 { 170 /* Nothing yet, perhaps we need something here later */ 171 return 0; 172 } 173 #endif /* CONFIG_ARCH_MISC_INIT */ 174 175 #ifdef CONFIG_MVNETA 176 int cpu_eth_init(bd_t *bis) 177 { 178 mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0); 179 mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1); 180 mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2); 181 mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3); 182 183 return 0; 184 } 185 #endif 186 187 #ifndef CONFIG_SYS_DCACHE_OFF 188 void enable_caches(void) 189 { 190 /* Enable D-cache. I-cache is already enabled in start.S */ 191 dcache_enable(); 192 } 193 #endif 194