1 /* 2 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <asm/io.h> 12 #include <asm/system.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 #include <asm/armv8/mmu.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* Armada 3700 */ 20 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800)) 21 22 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8) 23 #define MVEBU_XTAL_MODE_MASK BIT(9) 24 #define MVEBU_XTAL_MODE_OFFS 9 25 #define MVEBU_XTAL_CLOCK_25MHZ 0x0 26 #define MVEBU_XTAL_CLOCK_40MHZ 0x1 27 28 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40) 29 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e 30 31 static struct mm_region mvebu_mem_map[] = { 32 { 33 /* RAM */ 34 .phys = 0x0UL, 35 .virt = 0x0UL, 36 .size = 0x80000000UL, 37 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 38 PTE_BLOCK_INNER_SHARE 39 }, 40 { 41 /* SRAM, MMIO regions */ 42 .phys = 0xd0000000UL, 43 .virt = 0xd0000000UL, 44 .size = 0x02000000UL, /* 32MiB internal registers */ 45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 46 PTE_BLOCK_NON_SHARE 47 }, 48 { 49 /* List terminator */ 50 0, 51 } 52 }; 53 54 struct mm_region *mem_map = mvebu_mem_map; 55 56 /* 57 * On ARMv8, MBus is not configured in U-Boot. To enable compilation 58 * of the already implemented drivers, lets add a dummy version of 59 * this function so that linking does not fail. 60 */ 61 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) 62 { 63 return NULL; 64 } 65 66 void reset_cpu(ulong ignored) 67 { 68 /* 69 * Write magic number of 0x1d1e to North Bridge Warm Reset register 70 * to trigger warm reset 71 */ 72 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG); 73 } 74 75 /* 76 * get_ref_clk 77 * 78 * return: reference clock in MHz (25 or 40) 79 */ 80 u32 get_ref_clk(void) 81 { 82 u32 regval; 83 84 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> 85 MVEBU_XTAL_MODE_OFFS; 86 87 if (regval == MVEBU_XTAL_CLOCK_25MHZ) 88 return 25; 89 else 90 return 40; 91 } 92 93 /* DRAM init code ... */ 94 95 static const void *get_memory_reg_prop(const void *fdt, int *lenp) 96 { 97 int offset; 98 99 offset = fdt_path_offset(fdt, "/memory"); 100 if (offset < 0) 101 return NULL; 102 103 return fdt_getprop(fdt, offset, "reg", lenp); 104 } 105 106 int dram_init(void) 107 { 108 const void *fdt = gd->fdt_blob; 109 const fdt32_t *val; 110 int ac, sc, len; 111 112 ac = fdt_address_cells(fdt, 0); 113 sc = fdt_size_cells(fdt, 0); 114 if (ac < 0 || sc < 1 || sc > 2) { 115 printf("invalid address/size cells\n"); 116 return -EINVAL; 117 } 118 119 val = get_memory_reg_prop(fdt, &len); 120 if (len / sizeof(*val) < ac + sc) 121 return -EINVAL; 122 123 val += ac; 124 125 gd->ram_size = fdtdec_get_number(val, sc); 126 127 debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); 128 129 return 0; 130 } 131 132 void dram_init_banksize(void) 133 { 134 const void *fdt = gd->fdt_blob; 135 const fdt32_t *val; 136 int ac, sc, cells, len, i; 137 138 val = get_memory_reg_prop(fdt, &len); 139 if (len < 0) 140 return; 141 142 ac = fdt_address_cells(fdt, 0); 143 sc = fdt_size_cells(fdt, 0); 144 if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { 145 printf("invalid address/size cells\n"); 146 return; 147 } 148 149 cells = ac + sc; 150 151 len /= sizeof(*val); 152 153 for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; 154 i++, len -= cells) { 155 gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); 156 val += ac; 157 gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); 158 val += sc; 159 160 debug("DRAM bank %d: start = %08lx, size = %08lx\n", 161 i, (unsigned long)gd->bd->bi_dram[i].start, 162 (unsigned long)gd->bd->bi_dram[i].size); 163 } 164 } 165 166 int arch_cpu_init(void) 167 { 168 /* Nothing to do (yet) */ 169 return 0; 170 } 171 172 int arch_early_init_r(void) 173 { 174 struct udevice *dev; 175 int ret; 176 177 /* Call the comphy code via the MISC uclass driver */ 178 ret = uclass_get_device(UCLASS_MISC, 0, &dev); 179 if (ret) { 180 debug("COMPHY init failed: %d\n", ret); 181 return -ENODEV; 182 } 183 184 /* Cause the SATA device to do its early init */ 185 uclass_first_device(UCLASS_AHCI, &dev); 186 187 return 0; 188 } 189