1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dc7de222SMasahiro Yamada /* 3dc7de222SMasahiro Yamada * K2E: Clock management APIs 4dc7de222SMasahiro Yamada * 5dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 6dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 7dc7de222SMasahiro Yamada */ 8dc7de222SMasahiro Yamada 9dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_CLOCK_K2E_H 10dc7de222SMasahiro Yamada #define __ASM_ARCH_CLOCK_K2E_H 11dc7de222SMasahiro Yamada 12dc7de222SMasahiro Yamada #define PLLSET_CMD_LIST "<pa|ddr3>" 13dc7de222SMasahiro Yamada 14dc7de222SMasahiro Yamada #define KS2_CLK1_6 sys_clk0_6_clk 15dc7de222SMasahiro Yamada 16dc7de222SMasahiro Yamada #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} 17dc7de222SMasahiro Yamada #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} 18dc7de222SMasahiro Yamada #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} 19dc7de222SMasahiro Yamada #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} 20dc7de222SMasahiro Yamada #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} 21dc7de222SMasahiro Yamada #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} 22dc7de222SMasahiro Yamada #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} 23dc7de222SMasahiro Yamada #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} 24dc7de222SMasahiro Yamada #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} 25dc7de222SMasahiro Yamada #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 26dc7de222SMasahiro Yamada #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 27dc7de222SMasahiro Yamada #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 28dc7de222SMasahiro Yamada #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 29dc7de222SMasahiro Yamada 307b50e159SLokesh Vutla /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */ 317b50e159SLokesh Vutla #define DEV_SUPPORTED_SPEEDS 0xFFF 327b50e159SLokesh Vutla #define ARM_SUPPORTED_SPEEDS 0 337b50e159SLokesh Vutla 34dc7de222SMasahiro Yamada #endif 35