1 /* 2 * Keystone2: pll initialization 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/clock_defs.h> 13 14 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 15 int __weak speeds[DEVSPEED_NUMSPDS] = { 16 SPD1000, 17 SPD1200, 18 SPD1350, 19 SPD1400, 20 SPD1500, 21 SPD1400, 22 SPD1350, 23 SPD1200, 24 SPD1000, 25 SPD800, 26 }; 27 28 const struct keystone_pll_regs keystone_pll_regs[] = { 29 [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, 30 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, 31 [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, 32 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, 33 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, 34 }; 35 36 inline void pll_pa_clk_sel(void) 37 { 38 setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK); 39 } 40 41 static void wait_for_completion(const struct pll_init_data *data) 42 { 43 int i; 44 for (i = 0; i < 100; i++) { 45 sdelay(450); 46 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) 47 break; 48 } 49 } 50 51 static inline void bypass_main_pll(const struct pll_init_data *data) 52 { 53 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | 54 PLLCTL_PLLEN_MASK); 55 56 /* 4 cycles of reference clock CLKIN*/ 57 sdelay(340); 58 } 59 60 static void configure_mult_div(const struct pll_init_data *data) 61 { 62 u32 pllm, plld, bwadj; 63 64 pllm = data->pll_m - 1; 65 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; 66 67 /* Program Multiplier */ 68 if (data->pll == MAIN_PLL) 69 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); 70 71 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 72 CFG_PLLCTL0_PLLM_MASK, 73 pllm << CFG_PLLCTL0_PLLM_SHIFT); 74 75 /* Program BWADJ */ 76 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ 77 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 78 CFG_PLLCTL0_BWADJ_MASK, 79 (bwadj << CFG_PLLCTL0_BWADJ_SHIFT) & 80 CFG_PLLCTL0_BWADJ_MASK); 81 bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS; 82 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, 83 CFG_PLLCTL1_BWADJ_MASK, bwadj); 84 85 /* Program Divider */ 86 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 87 CFG_PLLCTL0_PLLD_MASK, plld); 88 } 89 90 void configure_main_pll(const struct pll_init_data *data) 91 { 92 u32 tmp, pllod, i, alnctl_val = 0; 93 u32 *offset; 94 95 pllod = data->pll_od - 1; 96 97 /* 100 micro sec for stabilization */ 98 sdelay(210000); 99 100 tmp = pllctl_reg_read(data->pll, secctl); 101 102 /* Check for Bypass */ 103 if (tmp & SECCTL_BYPASS_MASK) { 104 setbits_le32(keystone_pll_regs[data->pll].reg1, 105 CFG_PLLCTL1_ENSAT_MASK); 106 107 bypass_main_pll(data); 108 109 /* Powerdown and powerup Main Pll */ 110 pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK); 111 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 112 /* 5 micro sec */ 113 sdelay(21000); 114 115 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); 116 } else { 117 bypass_main_pll(data); 118 } 119 120 configure_mult_div(data); 121 122 /* Program Output Divider */ 123 pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK, 124 ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK)); 125 126 /* Program PLLDIVn */ 127 wait_for_completion(data); 128 for (i = 0; i < PLLDIV_MAX; i++) { 129 if (i < 3) 130 offset = pllctl_reg(data->pll, div1) + i; 131 else 132 offset = pllctl_reg(data->pll, div4) + (i - 3); 133 134 if (divn_val[i] != -1) { 135 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset); 136 alnctl_val |= BIT(i); 137 } 138 } 139 140 if (alnctl_val) { 141 pllctl_reg_setbits(data->pll, alnctl, alnctl_val); 142 /* 143 * Set GOSET bit in PLLCMD to initiate the GO operation 144 * to change the divide 145 */ 146 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK); 147 wait_for_completion(data); 148 } 149 150 /* Reset PLL */ 151 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 152 sdelay(21000); /* Wait for a minimum of 7 us*/ 153 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); 154 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ 155 156 /* Enable PLL */ 157 pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK); 158 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); 159 } 160 161 void configure_secondary_pll(const struct pll_init_data *data) 162 { 163 int pllod = data->pll_od - 1; 164 165 /* Enable Bypass mode */ 166 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); 167 setbits_le32(keystone_pll_regs[data->pll].reg0, 168 CFG_PLLCTL0_BYPASS_MASK); 169 170 /* Enable Glitch free bypass for ARM PLL */ 171 if (cpu_is_k2hk() && data->pll == TETRIS_PLL) 172 clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 173 174 configure_mult_div(data); 175 176 /* Program Output Divider */ 177 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, 178 CFG_PLLCTL0_CLKOD_MASK, 179 (pllod << CFG_PLLCTL0_CLKOD_SHIFT) & 180 CFG_PLLCTL0_CLKOD_MASK); 181 182 /* Reset PLL */ 183 setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 184 /* Wait for 5 micro seconds */ 185 sdelay(21000); 186 187 /* Select the Output of PASS PLL as input to PASS */ 188 if (data->pll == PASS_PLL && cpu_is_k2hk()) 189 pll_pa_clk_sel(); 190 191 /* Select the Output of ARM PLL as input to ARM */ 192 if (data->pll == TETRIS_PLL) 193 setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); 194 195 clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); 196 /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ 197 sdelay(105000); 198 199 /* Switch to PLL mode */ 200 clrbits_le32(keystone_pll_regs[data->pll].reg0, 201 CFG_PLLCTL0_BYPASS_MASK); 202 } 203 204 void init_pll(const struct pll_init_data *data) 205 { 206 if (data->pll == MAIN_PLL) 207 configure_main_pll(data); 208 else 209 configure_secondary_pll(data); 210 211 /* 212 * This is required to provide a delay between multiple 213 * consequent PPL configurations 214 */ 215 sdelay(210000); 216 } 217 218 void init_plls(void) 219 { 220 struct pll_init_data *data; 221 int pll; 222 223 for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) { 224 data = get_pll_init_data(pll); 225 if (data) 226 init_pll(data); 227 } 228 } 229 230 static int get_max_speed(u32 val, u32 speed_supported) 231 { 232 int speed; 233 234 /* Left most setbit gives the speed */ 235 for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) { 236 if ((val & BIT(speed)) & speed_supported) 237 return speeds[speed]; 238 } 239 240 /* If no bit is set, use SPD800 */ 241 return SPD800; 242 } 243 244 static inline u32 read_efuse_bootrom(void) 245 { 246 if (cpu_is_k2hk() && (cpu_revision() <= 1)) 247 return __raw_readl(KS2_REV1_DEVSPEED); 248 else 249 return __raw_readl(KS2_EFUSE_BOOTROM); 250 } 251 252 int get_max_arm_speed(void) 253 { 254 u32 armspeed = read_efuse_bootrom(); 255 256 armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >> 257 DEVSPEED_ARMSPEED_SHIFT; 258 259 return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS); 260 } 261 262 int get_max_dev_speed(void) 263 { 264 u32 devspeed = read_efuse_bootrom(); 265 266 devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >> 267 DEVSPEED_DEVSPEED_SHIFT; 268 269 return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS); 270 } 271 272 /** 273 * pll_freq_get - get pll frequency 274 * @pll: pll identifier 275 */ 276 static unsigned long pll_freq_get(int pll) 277 { 278 unsigned long mult = 1, prediv = 1, output_div = 2; 279 unsigned long ret; 280 u32 tmp, reg; 281 282 if (pll == MAIN_PLL) { 283 ret = external_clk[sys_clk]; 284 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { 285 /* PLL mode */ 286 tmp = __raw_readl(KS2_MAINPLLCTL0); 287 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 288 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >> 289 CFG_PLLCTL0_PLLM_SHIFT | 290 (pllctl_reg_read(pll, mult) & 291 PLLM_MULT_LO_MASK)) + 1; 292 output_div = ((pllctl_reg_read(pll, secctl) & 293 SECCTL_OP_DIV_MASK) >> 294 SECCTL_OP_DIV_SHIFT) + 1; 295 296 ret = ret / prediv / output_div * mult; 297 } 298 } else { 299 switch (pll) { 300 case PASS_PLL: 301 ret = external_clk[pa_clk]; 302 reg = KS2_PASSPLLCTL0; 303 break; 304 case TETRIS_PLL: 305 ret = external_clk[tetris_clk]; 306 reg = KS2_ARMPLLCTL0; 307 break; 308 case DDR3A_PLL: 309 ret = external_clk[ddr3a_clk]; 310 reg = KS2_DDR3APLLCTL0; 311 break; 312 case DDR3B_PLL: 313 ret = external_clk[ddr3b_clk]; 314 reg = KS2_DDR3BPLLCTL0; 315 break; 316 default: 317 return 0; 318 } 319 320 tmp = __raw_readl(reg); 321 322 if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) { 323 /* Bypass disabled */ 324 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1; 325 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >> 326 CFG_PLLCTL0_PLLM_SHIFT) + 1; 327 output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >> 328 CFG_PLLCTL0_CLKOD_SHIFT) + 1; 329 ret = ((ret / prediv) * mult) / output_div; 330 } 331 } 332 333 return ret; 334 } 335 336 unsigned long clk_get_rate(unsigned int clk) 337 { 338 unsigned long freq = 0; 339 340 switch (clk) { 341 case core_pll_clk: 342 freq = pll_freq_get(CORE_PLL); 343 break; 344 case pass_pll_clk: 345 freq = pll_freq_get(PASS_PLL); 346 break; 347 case tetris_pll_clk: 348 if (!cpu_is_k2e()) 349 freq = pll_freq_get(TETRIS_PLL); 350 break; 351 case ddr3a_pll_clk: 352 freq = pll_freq_get(DDR3A_PLL); 353 break; 354 case ddr3b_pll_clk: 355 if (cpu_is_k2hk()) 356 freq = pll_freq_get(DDR3B_PLL); 357 break; 358 case sys_clk0_1_clk: 359 case sys_clk0_clk: 360 freq = pll_freq_get(CORE_PLL) / pll0div_read(1); 361 break; 362 case sys_clk1_clk: 363 return pll_freq_get(CORE_PLL) / pll0div_read(2); 364 break; 365 case sys_clk2_clk: 366 freq = pll_freq_get(CORE_PLL) / pll0div_read(3); 367 break; 368 case sys_clk3_clk: 369 freq = pll_freq_get(CORE_PLL) / pll0div_read(4); 370 break; 371 case sys_clk0_2_clk: 372 freq = clk_get_rate(sys_clk0_clk) / 2; 373 break; 374 case sys_clk0_3_clk: 375 freq = clk_get_rate(sys_clk0_clk) / 3; 376 break; 377 case sys_clk0_4_clk: 378 freq = clk_get_rate(sys_clk0_clk) / 4; 379 break; 380 case sys_clk0_6_clk: 381 freq = clk_get_rate(sys_clk0_clk) / 6; 382 break; 383 case sys_clk0_8_clk: 384 freq = clk_get_rate(sys_clk0_clk) / 8; 385 break; 386 case sys_clk0_12_clk: 387 freq = clk_get_rate(sys_clk0_clk) / 12; 388 break; 389 case sys_clk0_24_clk: 390 freq = clk_get_rate(sys_clk0_clk) / 24; 391 break; 392 case sys_clk1_3_clk: 393 freq = clk_get_rate(sys_clk1_clk) / 3; 394 break; 395 case sys_clk1_4_clk: 396 freq = clk_get_rate(sys_clk1_clk) / 4; 397 break; 398 case sys_clk1_6_clk: 399 freq = clk_get_rate(sys_clk1_clk) / 6; 400 break; 401 case sys_clk1_12_clk: 402 freq = clk_get_rate(sys_clk1_clk) / 12; 403 break; 404 default: 405 break; 406 } 407 408 return freq; 409 } 410