xref: /openbmc/u-boot/arch/arm/mach-imx/speed.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2552a848eSStefano Babic /*
3552a848eSStefano Babic  * (C) Copyright 2000-2003
4552a848eSStefano Babic  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5552a848eSStefano Babic  *
6552a848eSStefano Babic  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7552a848eSStefano Babic  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8552a848eSStefano Babic  */
9552a848eSStefano Babic 
10552a848eSStefano Babic #include <common.h>
11552a848eSStefano Babic #include <asm/arch/imx-regs.h>
12552a848eSStefano Babic #include <asm/arch/clock.h>
13552a848eSStefano Babic 
14552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
15552a848eSStefano Babic DECLARE_GLOBAL_DATA_PTR;
16552a848eSStefano Babic #endif
17552a848eSStefano Babic 
get_clocks(void)18552a848eSStefano Babic int get_clocks(void)
19552a848eSStefano Babic {
20552a848eSStefano Babic #ifdef CONFIG_FSL_ESDHC
21552a848eSStefano Babic #ifdef CONFIG_FSL_USDHC
22552a848eSStefano Babic #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
23552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
24552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
25552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
26552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
27552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
28552a848eSStefano Babic #else
29552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
30552a848eSStefano Babic #endif
31552a848eSStefano Babic #else
32552a848eSStefano Babic #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
33552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
34552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
35552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
36552a848eSStefano Babic #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
37552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
38552a848eSStefano Babic #else
39552a848eSStefano Babic 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
40552a848eSStefano Babic #endif
41552a848eSStefano Babic #endif
42552a848eSStefano Babic #endif
43552a848eSStefano Babic 	return 0;
44552a848eSStefano Babic }
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