1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2552a848eSStefano Babic /* 3552a848eSStefano Babic * Copyright 2011 Freescale Semiconductor, Inc. 4552a848eSStefano Babic */ 5552a848eSStefano Babic 6552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 7552a848eSStefano Babic #include <asm/arch/iomux.h> 8552a848eSStefano Babic #include <asm/io.h> 9552a848eSStefano Babic #include <asm/arch/clock.h> 10552a848eSStefano Babic #include <asm/arch/sys_proto.h> 11552a848eSStefano Babic setup_sata(void)12552a848eSStefano Babicint setup_sata(void) 13552a848eSStefano Babic { 14552a848eSStefano Babic struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 15552a848eSStefano Babic int ret; 16552a848eSStefano Babic 17552a848eSStefano Babic if (!is_mx6dq() && !is_mx6dqp()) 18552a848eSStefano Babic return 1; 19552a848eSStefano Babic 20552a848eSStefano Babic ret = enable_sata_clock(); 21552a848eSStefano Babic if (ret) 22552a848eSStefano Babic return ret; 23552a848eSStefano Babic 24552a848eSStefano Babic clrsetbits_le32(&iomuxc_regs->gpr[13], 25552a848eSStefano Babic IOMUXC_GPR13_SATA_MASK, 26552a848eSStefano Babic IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB 27552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_7_SATA2M 28552a848eSStefano Babic |IOMUXC_GPR13_SATA_SPEED_3G 29552a848eSStefano Babic |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 30552a848eSStefano Babic |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED 31552a848eSStefano Babic |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 32552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB 33552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V 34552a848eSStefano Babic |IOMUXC_GPR13_SATA_PHY_1_SLOW); 35552a848eSStefano Babic 36552a848eSStefano Babic return 0; 37552a848eSStefano Babic } 38