1*57b62025SAnson Huang/* SPDX-License-Identifier: GPL-2.0+ */ 2*57b62025SAnson Huang/* 3*57b62025SAnson Huang * Copyright 2018 NXP 4*57b62025SAnson Huang */ 5*57b62025SAnson Huang 6*57b62025SAnson Huang#include <config.h> 7*57b62025SAnson Huang#include <linux/linkage.h> 8*57b62025SAnson Huang 9*57b62025SAnson Huang#include <asm/armv7.h> 10*57b62025SAnson Huang#include <asm/psci.h> 11*57b62025SAnson Huang 12*57b62025SAnson Huang .pushsection ._secure.text, "ax" 13*57b62025SAnson Huang 14*57b62025SAnson Huang .arch_extension sec 15*57b62025SAnson Huang 16*57b62025SAnson Huang.globl v7_invalidate_l1 17*57b62025SAnson Huangv7_invalidate_l1: 18*57b62025SAnson Huang mov r0, #0 19*57b62025SAnson Huang mcr p15, 2, r0, c0, c0, 0 20*57b62025SAnson Huang mrc p15, 1, r0, c0, c0, 0 21*57b62025SAnson Huang 22*57b62025SAnson Huang movw r1, #0x7fff 23*57b62025SAnson Huang and r2, r1, r0, lsr #13 24*57b62025SAnson Huang 25*57b62025SAnson Huang movw r1, #0x3ff 26*57b62025SAnson Huang 27*57b62025SAnson Huang and r3, r1, r0, lsr #3 @ NumWays - 1 28*57b62025SAnson Huang add r2, r2, #1 @ NumSets 29*57b62025SAnson Huang 30*57b62025SAnson Huang and r0, r0, #0x7 31*57b62025SAnson Huang add r0, r0, #4 @ SetShift 32*57b62025SAnson Huang 33*57b62025SAnson Huang clz r1, r3 @ WayShift 34*57b62025SAnson Huang add r4, r3, #1 @ NumWays 35*57b62025SAnson Huang1: 36*57b62025SAnson Huang sub r2, r2, #1 @ NumSets-- 37*57b62025SAnson Huang mov r3, r4 @ Temp = NumWays 38*57b62025SAnson Huang2: 39*57b62025SAnson Huang subs r3, r3, #1 @ Temp-- 40*57b62025SAnson Huang mov r5, r3, lsl r1 41*57b62025SAnson Huang mov r6, r2, lsl r0 42*57b62025SAnson Huang orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) 43*57b62025SAnson Huang mcr p15, 0, r5, c7, c6, 2 44*57b62025SAnson Huang bgt 2b 45*57b62025SAnson Huang cmp r2, #0 46*57b62025SAnson Huang bgt 1b 47*57b62025SAnson Huang dsb st 48*57b62025SAnson Huang isb 49*57b62025SAnson Huang mov pc, lr 50*57b62025SAnson Huang 51*57b62025SAnson Huang.globl psci_system_resume 52*57b62025SAnson Huangpsci_system_resume: 53*57b62025SAnson Huang mov sp, r0 54*57b62025SAnson Huang 55*57b62025SAnson Huang /* invalidate L1 I-cache first */ 56*57b62025SAnson Huang mov r6, #0x0 57*57b62025SAnson Huang mcr p15, 0, r6, c7, c5, 0 58*57b62025SAnson Huang mcr p15, 0, r6, c7, c5, 6 59*57b62025SAnson Huang /* enable the Icache and branch prediction */ 60*57b62025SAnson Huang mov r6, #0x1800 61*57b62025SAnson Huang mcr p15, 0, r6, c1, c0, 0 62*57b62025SAnson Huang isb 63*57b62025SAnson Huang 64*57b62025SAnson Huang bl v7_invalidate_l1 65*57b62025SAnson Huang b imx_system_resume 66*57b62025SAnson Huang 67*57b62025SAnson Huang .popsection 68