1 /* 2 * Copyright (C) 2018 Armadeus Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/crm_regs.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/gpio.h> 14 #include <asm/mach-imx/iomux-v3.h> 15 #include <asm/io.h> 16 #include <common.h> 17 #include <environment.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #ifdef CONFIG_FEC_MXC 22 #include <miiphy.h> 23 24 #define MDIO_PAD_CTRL ( \ 25 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 26 PAD_CTL_DSE_40ohm \ 27 ) 28 29 #define ENET_PAD_CTRL_PU ( \ 30 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 31 PAD_CTL_DSE_40ohm \ 32 ) 33 34 #define ENET_PAD_CTRL_PD ( \ 35 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm \ 37 ) 38 39 #define ENET_CLK_PAD_CTRL ( \ 40 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ 42 ) 43 44 static iomux_v3_cfg_t const fec1_pads[] = { 45 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 46 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), 47 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 48 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 49 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 50 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 51 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 52 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 53 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 54 /* PHY Int */ 55 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), 56 /* PHY Reset */ 57 MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), 58 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 59 }; 60 61 int board_phy_config(struct phy_device *phydev) 62 { 63 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 64 65 if (phydev->drv->config) 66 phydev->drv->config(phydev); 67 68 return 0; 69 } 70 71 int board_eth_init(bd_t *bis) 72 { 73 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 74 struct gpio_desc rst; 75 int ret; 76 77 /* Use 50M anatop loopback REF_CLK1 for ENET1, 78 * clear gpr1[13], set gpr1[17] */ 79 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 80 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 81 82 ret = enable_fec_anatop_clock(0, ENET_50MHZ); 83 if (ret) 84 return ret; 85 86 enable_enet_clk(1); 87 88 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 89 90 ret = dm_gpio_lookup_name("GPIO4_2", &rst); 91 if (ret) { 92 printf("Cannot get GPIO4_2\n"); 93 return ret; 94 } 95 96 ret = dm_gpio_request(&rst, "phy-rst"); 97 if (ret) { 98 printf("Cannot request GPIO4_2\n"); 99 return ret; 100 } 101 102 dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT); 103 dm_gpio_set_value(&rst, 0); 104 udelay(1000); 105 dm_gpio_set_value(&rst, 1); 106 107 return fecmxc_initialize(bis); 108 } 109 #endif /* CONFIG_FEC_MXC */ 110 111 int board_init(void) 112 { 113 /* Address of boot parameters */ 114 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 115 116 return 0; 117 } 118 119 int __weak opos6ul_board_late_init(void) 120 { 121 return 0; 122 } 123 124 int board_late_init(void) 125 { 126 struct src *psrc = (struct src *)SRC_BASE_ADDR; 127 unsigned reg = readl(&psrc->sbmr2); 128 129 /* In bootstrap don't use the env vars */ 130 if (((reg & 0x3000000) >> 24) == 0x1) { 131 set_default_env(NULL); 132 env_set("preboot", ""); 133 } 134 135 return opos6ul_board_late_init(); 136 } 137 138 int dram_init(void) 139 { 140 gd->ram_size = imx_ddr_size(); 141 142 return 0; 143 } 144 145 #ifdef CONFIG_SPL_BUILD 146 #include <asm/arch/mx6-ddr.h> 147 #include <linux/libfdt.h> 148 #include <spl.h> 149 150 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 151 .grp_addds = 0x00000030, 152 .grp_ddrmode_ctl = 0x00020000, 153 .grp_b0ds = 0x00000030, 154 .grp_ctlds = 0x00000030, 155 .grp_b1ds = 0x00000030, 156 .grp_ddrpke = 0x00000000, 157 .grp_ddrmode = 0x00020000, 158 .grp_ddr_type = 0x000c0000, 159 }; 160 161 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 162 .dram_dqm0 = 0x00000030, 163 .dram_dqm1 = 0x00000030, 164 .dram_ras = 0x00000030, 165 .dram_cas = 0x00000030, 166 .dram_odt0 = 0x00000030, 167 .dram_odt1 = 0x00000030, 168 .dram_sdba2 = 0x00000000, 169 .dram_sdclk_0 = 0x00000008, 170 .dram_sdqs0 = 0x00000038, 171 .dram_sdqs1 = 0x00000030, 172 .dram_reset = 0x00000030, 173 }; 174 175 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 176 .p0_mpwldectrl0 = 0x00070007, 177 .p0_mpdgctrl0 = 0x41490145, 178 .p0_mprddlctl = 0x40404546, 179 .p0_mpwrdlctl = 0x4040524D, 180 }; 181 182 struct mx6_ddr_sysinfo ddr_sysinfo = { 183 .dsize = 0, 184 .cs_density = 20, 185 .ncs = 1, 186 .cs1_mirror = 0, 187 .rtt_wr = 2, 188 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 189 .walat = 1, /* Write additional latency */ 190 .ralat = 5, /* Read additional latency */ 191 .mif3_mode = 3, /* Command prediction working mode */ 192 .bi_on = 1, /* Bank interleaving enabled */ 193 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 194 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 195 .ddr_type = DDR_TYPE_DDR3, 196 }; 197 198 static struct mx6_ddr3_cfg mem_ddr = { 199 .mem_speed = 800, 200 .density = 2, 201 .width = 16, 202 .banks = 8, 203 .rowaddr = 14, 204 .coladdr = 10, 205 .pagesz = 2, 206 .trcd = 1500, 207 .trcmin = 5250, 208 .trasmin = 3750, 209 }; 210 211 void board_boot_order(u32 *spl_boot_list) 212 { 213 unsigned int bmode = readl(&src_base->sbmr2); 214 215 if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */ 216 spl_boot_list[0] = BOOT_DEVICE_UART; 217 else 218 spl_boot_list[0] = spl_boot_device(); 219 } 220 221 static void ccgr_init(void) 222 { 223 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 224 225 writel(0xFFFFFFFF, &ccm->CCGR0); 226 writel(0xFFFFFFFF, &ccm->CCGR1); 227 writel(0xFFFFFFFF, &ccm->CCGR2); 228 writel(0xFFFFFFFF, &ccm->CCGR3); 229 writel(0xFFFFFFFF, &ccm->CCGR4); 230 writel(0xFFFFFFFF, &ccm->CCGR5); 231 writel(0xFFFFFFFF, &ccm->CCGR6); 232 writel(0xFFFFFFFF, &ccm->CCGR7); 233 } 234 235 static void spl_dram_init(void) 236 { 237 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; 238 struct fuse_bank *bank = &ocotp->bank[4]; 239 struct fuse_bank4_regs *fuse = 240 (struct fuse_bank4_regs *)bank->fuse_regs; 241 int reg = readl(&fuse->gp1); 242 243 /* 512MB of RAM */ 244 if (reg & 0x1) { 245 mem_ddr.density = 4; 246 mem_ddr.rowaddr = 15; 247 mem_ddr.trcd = 1375; 248 mem_ddr.trcmin = 4875; 249 mem_ddr.trasmin = 3500; 250 } 251 252 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 253 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 254 } 255 256 void spl_board_init(void) 257 { 258 preloader_console_init(); 259 } 260 261 void board_init_f(ulong dummy) 262 { 263 ccgr_init(); 264 265 /* setup AIPS and disable watchdog */ 266 arch_cpu_init(); 267 268 /* setup GP timer */ 269 timer_init(); 270 271 /* DDR initialization */ 272 spl_dram_init(); 273 } 274 #endif /* CONFIG_SPL_BUILD */ 275