xref: /openbmc/u-boot/arch/arm/mach-imx/ddrmc-vf610-calibration.h (revision b89074f65047c4058741ed2bf3e6ff0c5af4c5bc)
1*548cc109SLukasz Majewski /* SPDX-License-Identifier: GPL-2.0+ */
2*548cc109SLukasz Majewski /*
3*548cc109SLukasz Majewski  * ddrmc DDR3 calibration code for NXP's VF610
4*548cc109SLukasz Majewski  *
5*548cc109SLukasz Majewski  * Copyright (C) 2018 DENX Software Engineering
6*548cc109SLukasz Majewski  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7*548cc109SLukasz Majewski  *
8*548cc109SLukasz Majewski  */
9*548cc109SLukasz Majewski 
10*548cc109SLukasz Majewski #ifndef __DDRMC_VF610_CALIBRATOIN_H_
11*548cc109SLukasz Majewski #define __DDRMC_VF610_CALIBRATOIN_H_
12*548cc109SLukasz Majewski 
13*548cc109SLukasz Majewski /*
14*548cc109SLukasz Majewski  * Number of "samples" in the calibration bitmap
15*548cc109SLukasz Majewski  * to be considered during calibration.
16*548cc109SLukasz Majewski  */
17*548cc109SLukasz Majewski #define N_SAMPLES 3
18*548cc109SLukasz Majewski 
19*548cc109SLukasz Majewski /*
20*548cc109SLukasz Majewski  * Constants to indicate if we are looking for a rising or
21*548cc109SLukasz Majewski  * falling edge in the calibration bitmap
22*548cc109SLukasz Majewski  */
23*548cc109SLukasz Majewski enum edge {
24*548cc109SLukasz Majewski 	FALLING_EDGE = 1,
25*548cc109SLukasz Majewski 	RISING_EDGE
26*548cc109SLukasz Majewski };
27*548cc109SLukasz Majewski 
28*548cc109SLukasz Majewski /*
29*548cc109SLukasz Majewski  * The max number of delay elements when DQS to DQ setting
30*548cc109SLukasz Majewski  */
31*548cc109SLukasz Majewski #define DDRMC_DQS_DQ_MAX_DELAY 0xFF
32*548cc109SLukasz Majewski 
33*548cc109SLukasz Majewski /**
34*548cc109SLukasz Majewski  * ddrmc_calibration - Vybrid's (VF610) DDR3 calibration code
35*548cc109SLukasz Majewski  *
36*548cc109SLukasz Majewski  * This function is calculating proper memory controller values
37*548cc109SLukasz Majewski  * during run time.
38*548cc109SLukasz Majewski  *
39*548cc109SLukasz Majewski  * @param ddrmr_regs - memory controller registers
40*548cc109SLukasz Majewski  *
41*548cc109SLukasz Majewski  * @return 0 on success, otherwise error code
42*548cc109SLukasz Majewski  */
43*548cc109SLukasz Majewski int ddrmc_calibration(struct ddrmr_regs *ddrmr);
44*548cc109SLukasz Majewski 
45*548cc109SLukasz Majewski #endif /* __DDRMC_VF610_CALIBRATOIN_H_ */
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