1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23d357619SMasahiro Yamada /* 33d357619SMasahiro Yamada * Copyright (C) 2011 43d357619SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de. 53d357619SMasahiro Yamada */ 63d357619SMasahiro Yamada #ifndef _DV_DDR2_DEFS_H_ 73d357619SMasahiro Yamada #define _DV_DDR2_DEFS_H_ 83d357619SMasahiro Yamada 93d357619SMasahiro Yamada /* 103d357619SMasahiro Yamada * DDR2 Memory Ctrl Register structure 113d357619SMasahiro Yamada * See sprueh7d.pdf for more details. 123d357619SMasahiro Yamada */ 133d357619SMasahiro Yamada struct dv_ddr2_regs_ctrl { 143d357619SMasahiro Yamada unsigned char rsvd0[4]; /* 0x00 */ 153d357619SMasahiro Yamada unsigned int sdrstat; /* 0x04 */ 163d357619SMasahiro Yamada unsigned int sdbcr; /* 0x08 */ 173d357619SMasahiro Yamada unsigned int sdrcr; /* 0x0C */ 183d357619SMasahiro Yamada unsigned int sdtimr; /* 0x10 */ 193d357619SMasahiro Yamada unsigned int sdtimr2; /* 0x14 */ 203d357619SMasahiro Yamada unsigned char rsvd1[4]; /* 0x18 */ 213d357619SMasahiro Yamada unsigned int sdbcr2; /* 0x1C */ 223d357619SMasahiro Yamada unsigned int pbbpr; /* 0x20 */ 233d357619SMasahiro Yamada unsigned char rsvd2[156]; /* 0x24 */ 243d357619SMasahiro Yamada unsigned int irr; /* 0xC0 */ 253d357619SMasahiro Yamada unsigned int imr; /* 0xC4 */ 263d357619SMasahiro Yamada unsigned int imsr; /* 0xC8 */ 273d357619SMasahiro Yamada unsigned int imcr; /* 0xCC */ 283d357619SMasahiro Yamada unsigned char rsvd3[20]; /* 0xD0 */ 293d357619SMasahiro Yamada unsigned int ddrphycr; /* 0xE4 */ 303d357619SMasahiro Yamada unsigned int ddrphycr2; /* 0xE8 */ 313d357619SMasahiro Yamada unsigned char rsvd4[4]; /* 0xEC */ 323d357619SMasahiro Yamada }; 333d357619SMasahiro Yamada 343d357619SMasahiro Yamada #define DV_DDR_PHY_PWRDNEN 0x40 353d357619SMasahiro Yamada #define DV_DDR_PHY_EXT_STRBEN 0x80 363d357619SMasahiro Yamada #define DV_DDR_PHY_RD_LATENCY_SHIFT 0 373d357619SMasahiro Yamada 383d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RFC_SHIFT 25 393d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RP_SHIFT 22 403d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RCD_SHIFT 19 413d357619SMasahiro Yamada #define DV_DDR_SDTMR1_WR_SHIFT 16 423d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RAS_SHIFT 11 433d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RC_SHIFT 6 443d357619SMasahiro Yamada #define DV_DDR_SDTMR1_RRD_SHIFT 3 453d357619SMasahiro Yamada #define DV_DDR_SDTMR1_WTR_SHIFT 0 463d357619SMasahiro Yamada 473d357619SMasahiro Yamada #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 483d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XP_SHIFT 25 493d357619SMasahiro Yamada #define DV_DDR_SDTMR2_ODT_SHIFT 23 503d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XSNR_SHIFT 16 513d357619SMasahiro Yamada #define DV_DDR_SDTMR2_XSRD_SHIFT 8 523d357619SMasahiro Yamada #define DV_DDR_SDTMR2_RTP_SHIFT 5 533d357619SMasahiro Yamada #define DV_DDR_SDTMR2_CKE_SHIFT 0 543d357619SMasahiro Yamada 553d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR2TERM1_SHIFT 27 563d357619SMasahiro Yamada #define DV_DDR_SDCR_IBANK_POS_SHIFT 26 573d357619SMasahiro Yamada #define DV_DDR_SDCR_MSDRAMEN_SHIFT 25 583d357619SMasahiro Yamada #define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24 593d357619SMasahiro Yamada #define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23 603d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR_DDQS_SHIFT 22 613d357619SMasahiro Yamada #define DV_DDR_SDCR_DDR2EN_SHIFT 20 623d357619SMasahiro Yamada #define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18 633d357619SMasahiro Yamada #define DV_DDR_SDCR_DDREN_SHIFT 17 643d357619SMasahiro Yamada #define DV_DDR_SDCR_SDRAMEN_SHIFT 16 653d357619SMasahiro Yamada #define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15 663d357619SMasahiro Yamada #define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14 673d357619SMasahiro Yamada #define DV_DDR_SDCR_CL_SHIFT 9 683d357619SMasahiro Yamada #define DV_DDR_SDCR_IBANK_SHIFT 4 693d357619SMasahiro Yamada #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 703d357619SMasahiro Yamada 713d357619SMasahiro Yamada #define DV_DDR_SDRCR_LPMODEN (1 << 31) 723d357619SMasahiro Yamada #define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) 733d357619SMasahiro Yamada 743d357619SMasahiro Yamada #define DV_DDR_SRCR_LPMODEN_SHIFT 31 753d357619SMasahiro Yamada #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 763d357619SMasahiro Yamada 773d357619SMasahiro Yamada #define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT) 783d357619SMasahiro Yamada #define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) 793d357619SMasahiro Yamada 803d357619SMasahiro Yamada #define dv_ddr2_regs_ctrl \ 813d357619SMasahiro Yamada ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE) 823d357619SMasahiro Yamada 833d357619SMasahiro Yamada #endif /* _DV_DDR2_DEFS_H_ */ 84