1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
262011840SMasahiro Yamada /*
362011840SMasahiro Yamada * (C) Copyright 2014
462011840SMasahiro Yamada * Heiko Schocher, DENX Software Engineering, hs@denx.de.
562011840SMasahiro Yamada *
662011840SMasahiro Yamada * Based on:
762011840SMasahiro Yamada * (C) Copyright 2007-2008
862011840SMasahiro Yamada * Stelian Pop <stelian@popies.net>
962011840SMasahiro Yamada * Lead Tech Design <www.leadtechdesign.com>
1062011840SMasahiro Yamada */
1162011840SMasahiro Yamada
1262011840SMasahiro Yamada #include <common.h>
1362011840SMasahiro Yamada #include <asm/io.h>
1462011840SMasahiro Yamada #include <asm/arch/at91_common.h>
1562011840SMasahiro Yamada #include <asm/arch/at91sam9_sdramc.h>
1662011840SMasahiro Yamada #include <asm/arch/gpio.h>
1762011840SMasahiro Yamada
sdramc_initialize(unsigned int sdram_address,const struct sdramc_reg * p)1862011840SMasahiro Yamada int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p)
1962011840SMasahiro Yamada {
2062011840SMasahiro Yamada struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC;
2162011840SMasahiro Yamada unsigned int i;
2262011840SMasahiro Yamada
2362011840SMasahiro Yamada /* SDRAM feature must be in the configuration register */
2462011840SMasahiro Yamada writel(p->cr, ®->cr);
2562011840SMasahiro Yamada
2662011840SMasahiro Yamada /* The SDRAM memory type must be set in the Memory Device Register */
2762011840SMasahiro Yamada writel(p->mdr, ®->mdr);
2862011840SMasahiro Yamada
2962011840SMasahiro Yamada /*
3062011840SMasahiro Yamada * The minimum pause of 200 us is provided to precede any single
3162011840SMasahiro Yamada * toggle
3262011840SMasahiro Yamada */
3362011840SMasahiro Yamada for (i = 0; i < 1000; i++)
3462011840SMasahiro Yamada ;
3562011840SMasahiro Yamada
3662011840SMasahiro Yamada /* A NOP command is issued to the SDRAM devices */
3762011840SMasahiro Yamada writel(AT91_SDRAMC_MODE_NOP, ®->mr);
3862011840SMasahiro Yamada writel(0x00000000, sdram_address);
3962011840SMasahiro Yamada
4062011840SMasahiro Yamada /* An All Banks Precharge command is issued to the SDRAM devices */
4162011840SMasahiro Yamada writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr);
4262011840SMasahiro Yamada writel(0x00000000, sdram_address);
4362011840SMasahiro Yamada
4462011840SMasahiro Yamada for (i = 0; i < 10000; i++)
4562011840SMasahiro Yamada ;
4662011840SMasahiro Yamada
4762011840SMasahiro Yamada /* Eight auto-refresh cycles are provided */
4862011840SMasahiro Yamada for (i = 0; i < 8; i++) {
4962011840SMasahiro Yamada writel(AT91_SDRAMC_MODE_REFRESH, ®->mr);
5062011840SMasahiro Yamada writel(0x00000001 + i, sdram_address + 4 + 4 * i);
5162011840SMasahiro Yamada }
5262011840SMasahiro Yamada
5362011840SMasahiro Yamada /*
5462011840SMasahiro Yamada * A Mode Register set (MRS) cyscle is issued to program the
5562011840SMasahiro Yamada * SDRAM parameters(TCSR, PASR, DS)
5662011840SMasahiro Yamada */
5762011840SMasahiro Yamada writel(AT91_SDRAMC_MODE_LMR, ®->mr);
5862011840SMasahiro Yamada writel(0xcafedede, sdram_address + 0x24);
5962011840SMasahiro Yamada
6062011840SMasahiro Yamada /*
6162011840SMasahiro Yamada * The application must go into Normal Mode, setting Mode
6262011840SMasahiro Yamada * to 0 in the Mode Register and perform a write access at
6362011840SMasahiro Yamada * any location in the SDRAM.
6462011840SMasahiro Yamada */
6562011840SMasahiro Yamada writel(AT91_SDRAMC_MODE_NORMAL, ®->mr);
6662011840SMasahiro Yamada writel(0x00000000, sdram_address); /* Perform Normal mode */
6762011840SMasahiro Yamada
6862011840SMasahiro Yamada /*
6962011840SMasahiro Yamada * Write the refresh rate into the count field in the SDRAMC
7062011840SMasahiro Yamada * Refresh Timer Rgister.
7162011840SMasahiro Yamada */
7262011840SMasahiro Yamada writel(p->tr, ®->tr);
7362011840SMasahiro Yamada
7462011840SMasahiro Yamada return 0;
7562011840SMasahiro Yamada }
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