1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h] 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2007 Atmel Corporation 5*af930827SMasahiro Yamada * 6*af930827SMasahiro Yamada * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7*af930827SMasahiro Yamada * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8*af930827SMasahiro Yamada * 9*af930827SMasahiro Yamada * This file is subject to the terms and conditions of the GNU General Public 10*af930827SMasahiro Yamada * License. See the file COPYING in the main directory of this archive for 11*af930827SMasahiro Yamada * more details. 12*af930827SMasahiro Yamada */ 13*af930827SMasahiro Yamada 14*af930827SMasahiro Yamada #ifndef AT91SAM9RL_MATRIX_H 15*af930827SMasahiro Yamada #define AT91SAM9RL_MATRIX_H 16*af930827SMasahiro Yamada 17*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 18*af930827SMasahiro Yamada 19*af930827SMasahiro Yamada struct at91_matrix { 20*af930827SMasahiro Yamada u32 mcfg[16]; /* Master Configuration Registers */ 21*af930827SMasahiro Yamada u32 scfg[16]; /* Slave Configuration Registers */ 22*af930827SMasahiro Yamada u32 pras[16][2]; /* Priority Assignment Slave Registers */ 23*af930827SMasahiro Yamada u32 mrcr; /* Master Remap Control Register */ 24*af930827SMasahiro Yamada u32 filler[7]; 25*af930827SMasahiro Yamada u32 ebicsa; /* EBI Chip Select Assignment Register */ 26*af930827SMasahiro Yamada }; 27*af930827SMasahiro Yamada 28*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 29*af930827SMasahiro Yamada 30*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 31*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 32*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_FOUR (2 << 0) 33*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 34*af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 35*af930827SMasahiro Yamada 36*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 37*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 38*af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 39*af930827SMasahiro Yamada #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 40*af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 41*af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 42*af930827SMasahiro Yamada 43*af930827SMasahiro Yamada #define AT91_MATRIX_M0PR_SHIFT 0 44*af930827SMasahiro Yamada #define AT91_MATRIX_M1PR_SHIFT 4 45*af930827SMasahiro Yamada #define AT91_MATRIX_M2PR_SHIFT 8 46*af930827SMasahiro Yamada #define AT91_MATRIX_M3PR_SHIFT 12 47*af930827SMasahiro Yamada #define AT91_MATRIX_M4PR_SHIFT 16 48*af930827SMasahiro Yamada #define AT91_MATRIX_M5PR_SHIFT 20 49*af930827SMasahiro Yamada 50*af930827SMasahiro Yamada #define AT91_MATRIX_RCB0 (1 << 0) 51*af930827SMasahiro Yamada #define AT91_MATRIX_RCB1 (1 << 1) 52*af930827SMasahiro Yamada 53*af930827SMasahiro Yamada #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 54*af930827SMasahiro Yamada #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 55*af930827SMasahiro Yamada #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 56*af930827SMasahiro Yamada #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 57*af930827SMasahiro Yamada #define AT91_MATRIX_DBPUC (1 << 8) 58*af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 59*af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 60*af930827SMasahiro Yamada 61*af930827SMasahiro Yamada #endif 62