xref: /openbmc/u-boot/arch/arm/mach-at91/include/mach/at91_rstc.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2af930827SMasahiro Yamada /*
3af930827SMasahiro Yamada  * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
4af930827SMasahiro Yamada  *
5af930827SMasahiro Yamada  * Copyright (C) 2007 Andrew Victor
6af930827SMasahiro Yamada  * Copyright (C) 2007 Atmel Corporation.
7af930827SMasahiro Yamada  *
8af930827SMasahiro Yamada  * Reset Controller (RSTC) - System peripherals regsters.
9af930827SMasahiro Yamada  * Based on AT91SAM9261 datasheet revision D.
10af930827SMasahiro Yamada  */
11af930827SMasahiro Yamada 
12af930827SMasahiro Yamada #ifndef AT91_RSTC_H
13af930827SMasahiro Yamada #define AT91_RSTC_H
14af930827SMasahiro Yamada 
15af930827SMasahiro Yamada /* Reset Controller Status Register */
16af930827SMasahiro Yamada #define AT91_ASM_RSTC_SR	(ATMEL_BASE_RSTC + 0x04)
17af930827SMasahiro Yamada #define AT91_ASM_RSTC_MR	(ATMEL_BASE_RSTC + 0x08)
18af930827SMasahiro Yamada 
19af930827SMasahiro Yamada #ifndef __ASSEMBLY__
20af930827SMasahiro Yamada 
21af930827SMasahiro Yamada typedef struct at91_rstc {
22af930827SMasahiro Yamada 	u32	cr;	/* Reset Controller Control Register */
23af930827SMasahiro Yamada 	u32	sr;	/* Reset Controller Status Register */
24af930827SMasahiro Yamada 	u32	mr;	/* Reset Controller Mode Register */
25af930827SMasahiro Yamada } at91_rstc_t;
26af930827SMasahiro Yamada 
27af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */
28af930827SMasahiro Yamada 
29af930827SMasahiro Yamada #define AT91_RSTC_KEY		0xA5000000
30af930827SMasahiro Yamada 
31af930827SMasahiro Yamada #define AT91_RSTC_CR_PROCRST	0x00000001
32af930827SMasahiro Yamada #define AT91_RSTC_CR_PERRST	0x00000004
33af930827SMasahiro Yamada #define AT91_RSTC_CR_EXTRST	0x00000008
34af930827SMasahiro Yamada 
35af930827SMasahiro Yamada #define AT91_RSTC_MR_URSTEN	0x00000001
36af930827SMasahiro Yamada #define AT91_RSTC_MR_URSTIEN	0x00000010
37af930827SMasahiro Yamada #define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
38af930827SMasahiro Yamada #define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
39af930827SMasahiro Yamada 
40af930827SMasahiro Yamada #define AT91_RSTC_SR_NRSTL	0x00010000
41af930827SMasahiro Yamada 
42af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
43af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
44af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_WAKEUP	(1 << 8)
45af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
46af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
47af930827SMasahiro Yamada #define AT91_RSTC_RSTTYP_USER		(4 << 8)
48af930827SMasahiro Yamada 
49af930827SMasahiro Yamada #endif
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