xref: /openbmc/u-boot/arch/arm/mach-aspeed/ast2600/scu_info.c (revision eaad4c09196116841f5914deba2321c3c38f4fa0) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  */
6 
7 #include <common.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <asm/arch/aspeed_scu_info.h>
11 
12 /* SoC mapping Table */
13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
14 
15 struct soc_id {
16 	const char *name;
17 	u64 rev_id;
18 };
19 
20 static struct soc_id soc_map_table[] = {
21 	SOC_ID("AST2600-A0", 0x0500030305000303),
22 	SOC_ID("AST2600-A1", 0x0501030305010303),
23 	SOC_ID("AST2620-A1", 0x0501020305010203),
24 	SOC_ID("AST2600-A2", 0x0502030305010303),
25 	SOC_ID("AST2620-A2", 0x0502020305010203),
26 	SOC_ID("AST2605-A2", 0x0502010305010103),
27 	SOC_ID("AST2600-A3", 0x0503030305030303),
28 	SOC_ID("AST2620-A3", 0x0503020305030203),
29 	SOC_ID("AST2605-A3", 0x0503010305030103),
30 	SOC_ID("AST2625-A3", 0x0503040305030403),
31 };
32 
33 void aspeed_print_soc_id(void)
34 {
35 	int i;
36 	u64 rev_id;
37 
38 	rev_id = readl(ASPEED_REVISION_ID0);
39 	rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id;
40 
41 	for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) {
42 		if (rev_id == soc_map_table[i].rev_id)
43 			break;
44 	}
45 	if (i == ARRAY_SIZE(soc_map_table))
46 		printf("UnKnow-SOC: %llx\n", rev_id);
47 	else
48 		printf("SOC: %4s \n",soc_map_table[i].name);
49 }
50 
51 int aspeed_get_mac_phy_interface(u8 num)
52 {
53 	u32 strap1 = readl(ASPEED_HW_STRAP1);
54 #ifdef ASPEED_HW_STRAP2
55 	u32 strap2 = readl(ASPEED_HW_STRAP2);
56 #endif
57 	switch(num) {
58 		case 0:
59 			if(strap1 & BIT(6)) {
60 				return 1;
61 			} else {
62 				return 0;
63 			}
64 			break;
65 		case 1:
66 			if(strap1 & BIT(7)) {
67 				return 1;
68 			} else {
69 				return 0;
70 			}
71 			break;
72 #ifdef ASPEED_HW_STRAP2
73 		case 2:
74 			if(strap2 & BIT(0)) {
75 				return 1;
76 			} else {
77 				return 0;
78 			}
79 			break;
80 		case 3:
81 			if(strap2 & BIT(1)) {
82 				return 1;
83 			} else {
84 				return 0;
85 			}
86 			break;
87 #endif
88 	}
89 	return -1;
90 }
91 
92 void aspeed_print_security_info(void)
93 {
94 	u32 qsr = readl(ASPEED_OTP_QSR);
95 	u32 sb_sts = readl(ASPEED_SB_STS);
96 	u32 hash;
97 	u32 rsa;
98 
99 	if (!(sb_sts & BIT(6)))
100 		return;
101 	printf("Secure Boot: ");
102 	if (qsr & BIT(7)) {
103 		hash = (qsr >> 10) & 3;
104 		rsa = (qsr >> 12) & 3;
105 
106 		printf("Mode_2, ");
107 
108 		if (qsr & BIT(27)) {
109 			printf("AES_");
110 		}
111 		switch (rsa) {
112 		case 0:
113 			printf("RSA1024_");
114 			break;
115 		case 1:
116 			printf("RSA2048_");
117 			break;
118 		case 2:
119 			printf("RSA3072_");
120 			break;
121 		default:
122 			printf("RSA4096_");
123 			break;
124 		}
125 		switch (hash) {
126 		case 0:
127 			printf("SHA224\n");
128 			break;
129 		case 1:
130 			printf("SHA256\n");
131 			break;
132 		case 2:
133 			printf("SHA384\n");
134 			break;
135 		default:
136 			printf("SHA512\n");
137 			break;
138 		}
139 	} else {
140 		printf("Mode_GCM\n");
141 		return;
142 	}
143 }
144 
145 /*	ASPEED_SYS_RESET_CTRL	: System reset contrl/status register*/
146 #define SYS_WDT8_SW_RESET	BIT(15)
147 #define SYS_WDT8_ARM_RESET	BIT(14)
148 #define SYS_WDT8_FULL_RESET	BIT(13)
149 #define SYS_WDT8_SOC_RESET	BIT(12)
150 #define SYS_WDT7_SW_RESET	BIT(11)
151 #define SYS_WDT7_ARM_RESET	BIT(10)
152 #define SYS_WDT7_FULL_RESET	BIT(9)
153 #define SYS_WDT7_SOC_RESET	BIT(8)
154 #define SYS_WDT6_SW_RESET	BIT(7)
155 #define SYS_WDT6_ARM_RESET	BIT(6)
156 #define SYS_WDT6_FULL_RESET	BIT(5)
157 #define SYS_WDT6_SOC_RESET	BIT(4)
158 #define SYS_WDT5_SW_RESET	BIT(3)
159 #define SYS_WDT5_ARM_RESET	BIT(2)
160 #define SYS_WDT5_FULL_RESET	BIT(1)
161 #define SYS_WDT5_SOC_RESET	BIT(0)
162 
163 #define SYS_WDT4_SW_RESET	BIT(31)
164 #define SYS_WDT4_ARM_RESET	BIT(30)
165 #define SYS_WDT4_FULL_RESET	BIT(29)
166 #define SYS_WDT4_SOC_RESET	BIT(28)
167 #define SYS_WDT3_SW_RESET	BIT(27)
168 #define SYS_WDT3_ARM_RESET	BIT(26)
169 #define SYS_WDT3_FULL_RESET	BIT(25)
170 #define SYS_WDT3_SOC_RESET	BIT(24)
171 #define SYS_WDT2_SW_RESET	BIT(23)
172 #define SYS_WDT2_ARM_RESET	BIT(22)
173 #define SYS_WDT2_FULL_RESET	BIT(21)
174 #define SYS_WDT2_SOC_RESET	BIT(20)
175 #define SYS_WDT1_SW_RESET	BIT(19)
176 #define SYS_WDT1_ARM_RESET	BIT(18)
177 #define SYS_WDT1_FULL_RESET	BIT(17)
178 #define SYS_WDT1_SOC_RESET	BIT(16)
179 
180 #define SYS_CM3_EXT_RESET	BIT(6)
181 #define SYS_PCI2_RESET		BIT(5)
182 #define SYS_PCI1_RESET		BIT(4)
183 #define SYS_DRAM_ECC_RESET	BIT(3)
184 #define SYS_FLASH_ABR_RESET	BIT(2)
185 #define SYS_EXT_RESET		BIT(1)
186 #define SYS_PWR_RESET_FLAG	BIT(0)
187 
188 #define BIT_WDT_SOC(x)	SYS_WDT ## x ## _SOC_RESET
189 #define BIT_WDT_FULL(x)	SYS_WDT ## x ## _FULL_RESET
190 #define BIT_WDT_ARM(x)	SYS_WDT ## x ## _ARM_RESET
191 #define BIT_WDT_SW(x)	SYS_WDT ## x ## _SW_RESET
192 
193 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \
194 	if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \
195 		printf("RST: WDT%d ", x); \
196 		if (event_log & BIT_WDT_SOC(x)) { \
197 			printf("SOC "); \
198 			writel(BIT_WDT_SOC(x), event_log_reg); \
199 		} \
200 		if (event_log & BIT_WDT_FULL(x)) { \
201 			printf("FULL "); \
202 			writel(BIT_WDT_FULL(x), event_log_reg); \
203 		} \
204 		if (event_log & BIT_WDT_ARM(x)) { \
205 			printf("ARM "); \
206 			writel(BIT_WDT_ARM(x), event_log_reg); \
207 		} \
208 		if (event_log & BIT_WDT_SW(x)) { \
209 			printf("SW "); \
210 			writel(BIT_WDT_SW(x), event_log_reg); \
211 		} \
212 		printf("\n"); \
213 	} \
214 	(void)(x)
215 
216 void aspeed_print_sysrst_info(void)
217 {
218 	u32 rest = readl(ASPEED_SYS_RESET_CTRL);
219 	u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3);
220 
221 	if (rest & SYS_PWR_RESET_FLAG) {
222 		printf("RST: Power On \n");
223 		writel(rest, ASPEED_SYS_RESET_CTRL);
224 	} else {
225 		HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3);
226 		HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3);
227 		HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3);
228 		HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3);
229 		HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL);
230 		HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL);
231 		HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL);
232 		HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL);
233 
234 		if (rest & SYS_CM3_EXT_RESET) {
235 			printf("RST: SYS_CM3_EXT_RESET \n");
236 			writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL);
237 		}
238 
239 		if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) {
240 			printf("PCI RST: ");
241 			if (rest & SYS_PCI1_RESET) {
242 				printf("#1 ");
243 				writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL);
244 			}
245 
246 			if (rest & SYS_PCI2_RESET) {
247 				printf("#2 ");
248 				writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL);
249 			}
250 			printf("\n");
251 		}
252 
253 		if (rest & SYS_DRAM_ECC_RESET) {
254 			printf("RST: DRAM_ECC_RESET \n");
255 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
256 		}
257 
258 		if (rest & SYS_FLASH_ABR_RESET) {
259 			printf("RST: SYS_FLASH_ABR_RESET \n");
260 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
261 		}
262 		if (rest & SYS_EXT_RESET) {
263 			printf("RST: External \n");
264 			writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL);
265 		}
266 	}
267 }
268 
269 #define SOC_FW_INIT_DRAM		BIT(7)
270 
271 void aspeed_print_dram_initializer(void)
272 {
273 	if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM)
274 		printf("[init by SOC]\n");
275 	else
276 		printf("[init by VBIOS]\n");
277 }
278 
279 void aspeed_print_2nd_wdt_mode(void)
280 {
281 	/* ABR enable */
282 	if (readl(ASPEED_HW_STRAP2) & BIT(11)) {
283 		/* boot from eMMC */
284 		if (readl(ASPEED_HW_STRAP1) & BIT(2)) {
285 			printf("eMMC 2nd Boot (ABR): Enable");
286 			printf(", boot partition: %s", \
287 				readl(ASPEED_EMMC_WDT_CTRL) & BIT(4) ? "2" : "1");
288 			printf("\n");
289 		} else { /* boot from SPI */
290 			printf("FMC 2nd Boot (ABR): Enable");
291 			if (readl(ASPEED_HW_STRAP2) & BIT(12))
292 				printf(", Single flash");
293 			else
294 				printf(", Dual flashes");
295 
296 			printf(", Source: %s", \
297 					readl(ASPEED_FMC_WDT2) & BIT(4) ? "Alternate" : "Primary");
298 
299 			if (readl(ASPEED_HW_STRAP2) & GENMASK(15, 13))
300 				printf(", bspi_size: %ld MB", \
301 					BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7));
302 
303 			printf("\n");
304 		}
305 	}
306 }
307 
308 void aspeed_print_fmc_aux_ctrl(void)
309 {
310 
311 	if (readl(ASPEED_HW_STRAP2) & BIT(22)) {
312 		printf("FMC aux control: Enable");
313 		/* gpioY6 : BSPI_ABR */
314 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(6))
315 			printf(", Force Alt boot");
316 
317 		/* gpioY7 : BSPI_WP_N */
318 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)))
319 			printf(", BSPI_WP: Enable");
320 
321 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)) && \
322 			(readl(ASPEED_HW_STRAP2) & GENMASK(24, 23)) != 0) {
323 			printf(", FMC HW CRTM: Enable, size: %ld KB", \
324 					BIT((readl(ASPEED_HW_STRAP2) >> 23) & 0x3) * 128);
325 		}
326 
327 		printf("\n");
328 	}
329 }
330 
331 void aspeed_print_spi1_abr_mode(void)
332 {
333 	if (readl(ASPEED_HW_STRAP2) & BIT(16)) {
334 		printf("SPI1 ABR: Enable");
335 		if(readl(ASPEED_SPI1_BOOT_CTRL) & BIT(6))
336 			printf(", Single flash");
337 		else
338 			printf(", Dual flashes");
339 
340 		printf(", Source : %s", \
341 				readl(ASPEED_SPI1_BOOT_CTRL) & BIT(4) ? "Alternate" : "Primary");
342 
343 		if (readl(ASPEED_SPI1_BOOT_CTRL) & GENMASK(3, 1))
344 			printf(", hspi_size : %ld MB", \
345 				BIT((readl(ASPEED_SPI1_BOOT_CTRL) >> 1) & 0x7));
346 
347 		printf("\n");
348 	}
349 
350 	if (readl(ASPEED_HW_STRAP2) & BIT(17)) {
351 		printf("SPI1 select pin: Enable");
352 		/* gpioZ1 : HSPI_ABR */
353 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
354 			printf(", Force Alt boot");
355 
356 		printf("\n");
357 	}
358 }
359 
360 void aspeed_print_spi1_aux_ctrl(void)
361 {
362 	if (readl(ASPEED_HW_STRAP2) & BIT(27)) {
363 		printf("SPI1 aux control: Enable");
364 		/* gpioZ1 : HSPI_ABR */
365 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
366 			printf(", Force Alt boot");
367 
368 		/* gpioZ2: BSPI_WP_N */
369 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)))
370 			printf(", HPI_WP: Enable");
371 
372 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)) && \
373 			(readl(ASPEED_HW_STRAP2) & GENMASK(26, 25)) != 0) {
374 			printf(", SPI1 HW CRTM: Enable, size: %ld KB", \
375 					BIT((readl(ASPEED_HW_STRAP2) >> 25) & 0x3) * 128);
376 		}
377 
378 		printf("\n");
379 	}
380 }
381 
382 void aspeed_print_spi_strap_mode(void)
383 {
384 	if(readl(ASPEED_HW_STRAP2) & BIT(10))
385 		printf("SPI: 3/4 byte mode auto detection \n");
386 }
387 
388 void aspeed_print_espi_mode(void)
389 {
390 	int espi_mode = 0;
391 	int sio_disable = 0;
392 	u32 sio_addr = 0x2e;
393 
394 	if (readl(ASPEED_HW_STRAP2) & BIT(6))
395 		espi_mode = 0;
396 	else
397 		espi_mode = 1;
398 
399 	if (readl(ASPEED_HW_STRAP2) & BIT(2))
400 		sio_addr = 0x4e;
401 
402 	if (readl(ASPEED_HW_STRAP2) & BIT(3))
403 		sio_disable = 1;
404 
405 	if (espi_mode)
406 		printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
407 	else
408 		printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
409 
410 	if (!sio_disable)
411 		printf(": SuperIO-%02x\n", sio_addr);
412 	else
413 		printf("\n");
414 }
415 
416 void aspeed_print_mac_info(void)
417 {
418 	int i;
419 	printf("Eth: ");
420 	for (i = 0; i < ASPEED_MAC_COUNT; i++) {
421 		printf("MAC%d: %s", i,
422 				aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI");
423 		if (i != (ASPEED_MAC_COUNT -1))
424 			printf(", ");
425 	}
426 	printf("\n");
427 }
428