1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <asm/io.h> 10 #include <asm/arch/aspeed_scu_info.h> 11 12 /* SoC mapping Table */ 13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, } 14 15 struct soc_id { 16 const char *name; 17 u64 rev_id; 18 }; 19 20 static struct soc_id soc_map_table[] = { 21 SOC_ID("AST2600-A0", 0x0500030305000303), 22 SOC_ID("AST2600-A1", 0x0501030305010303), 23 SOC_ID("AST2620-A1", 0x0501020305010203), 24 SOC_ID("AST2600-A2", 0x0502030305010303), 25 SOC_ID("AST2620-A2", 0x0502020305010203), 26 SOC_ID("AST2605-A2", 0x0502010305010103), 27 }; 28 29 void aspeed_print_soc_id(void) 30 { 31 int i; 32 u64 rev_id; 33 34 rev_id = readl(ASPEED_REVISION_ID0); 35 rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id; 36 37 for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { 38 if (rev_id == soc_map_table[i].rev_id) 39 break; 40 } 41 if (i == ARRAY_SIZE(soc_map_table)) 42 printf("UnKnow-SOC: %llx\n", rev_id); 43 else 44 printf("SOC: %4s \n",soc_map_table[i].name); 45 } 46 47 int aspeed_get_mac_phy_interface(u8 num) 48 { 49 u32 strap1 = readl(ASPEED_HW_STRAP1); 50 #ifdef ASPEED_HW_STRAP2 51 u32 strap2 = readl(ASPEED_HW_STRAP2); 52 #endif 53 switch(num) { 54 case 0: 55 if(strap1 & BIT(6)) { 56 return 1; 57 } else { 58 return 0; 59 } 60 break; 61 case 1: 62 if(strap1 & BIT(7)) { 63 return 1; 64 } else { 65 return 0; 66 } 67 break; 68 #ifdef ASPEED_HW_STRAP2 69 case 2: 70 if(strap2 & BIT(0)) { 71 return 1; 72 } else { 73 return 0; 74 } 75 break; 76 case 3: 77 if(strap2 & BIT(1)) { 78 return 1; 79 } else { 80 return 0; 81 } 82 break; 83 #endif 84 } 85 return -1; 86 } 87 88 void aspeed_print_security_info(void) 89 { 90 u32 qsr = readl(ASPEED_OTP_QSR); 91 u32 sb_sts = readl(ASPEED_SB_STS); 92 u32 hash; 93 u32 rsa; 94 char alg[20]; 95 96 if (!(sb_sts & BIT(6))) 97 return; 98 printf("Secure Boot: "); 99 if (qsr & BIT(7)) { 100 hash = (qsr >> 10) & 3; 101 rsa = (qsr >> 12) & 3; 102 103 if (qsr & BIT(27)) { 104 sprintf(alg + strlen(alg), "AES_"); 105 } 106 switch (rsa) { 107 case 0: 108 sprintf(alg + strlen(alg), "RSA1024_"); 109 break; 110 case 1: 111 sprintf(alg + strlen(alg), "RSA2048_"); 112 break; 113 case 2: 114 sprintf(alg + strlen(alg), "RSA3072_"); 115 break; 116 default: 117 sprintf(alg + strlen(alg), "RSA4096_"); 118 break; 119 } 120 switch (hash) { 121 case 0: 122 sprintf(alg + strlen(alg), "SHA224"); 123 break; 124 case 1: 125 sprintf(alg + strlen(alg), "SHA256"); 126 break; 127 case 2: 128 sprintf(alg + strlen(alg), "SHA384"); 129 break; 130 default: 131 sprintf(alg + strlen(alg), "SHA512"); 132 break; 133 } 134 printf("Mode_2, %s\n", alg); 135 } else { 136 printf("Mode_GCM\n"); 137 return; 138 } 139 } 140 141 /* ASPEED_SYS_RESET_CTRL : System reset contrl/status register*/ 142 #define SYS_WDT8_SW_RESET BIT(15) 143 #define SYS_WDT8_ARM_RESET BIT(14) 144 #define SYS_WDT8_FULL_RESET BIT(13) 145 #define SYS_WDT8_SOC_RESET BIT(12) 146 #define SYS_WDT7_SW_RESET BIT(11) 147 #define SYS_WDT7_ARM_RESET BIT(10) 148 #define SYS_WDT7_FULL_RESET BIT(9) 149 #define SYS_WDT7_SOC_RESET BIT(8) 150 #define SYS_WDT6_SW_RESET BIT(7) 151 #define SYS_WDT6_ARM_RESET BIT(6) 152 #define SYS_WDT6_FULL_RESET BIT(5) 153 #define SYS_WDT6_SOC_RESET BIT(4) 154 #define SYS_WDT5_SW_RESET BIT(3) 155 #define SYS_WDT5_ARM_RESET BIT(2) 156 #define SYS_WDT5_FULL_RESET BIT(1) 157 #define SYS_WDT5_SOC_RESET BIT(0) 158 159 #define SYS_WDT4_SW_RESET BIT(31) 160 #define SYS_WDT4_ARM_RESET BIT(30) 161 #define SYS_WDT4_FULL_RESET BIT(29) 162 #define SYS_WDT4_SOC_RESET BIT(28) 163 #define SYS_WDT3_SW_RESET BIT(27) 164 #define SYS_WDT3_ARM_RESET BIT(26) 165 #define SYS_WDT3_FULL_RESET BIT(25) 166 #define SYS_WDT3_SOC_RESET BIT(24) 167 #define SYS_WDT2_SW_RESET BIT(23) 168 #define SYS_WDT2_ARM_RESET BIT(22) 169 #define SYS_WDT2_FULL_RESET BIT(21) 170 #define SYS_WDT2_SOC_RESET BIT(20) 171 #define SYS_WDT1_SW_RESET BIT(19) 172 #define SYS_WDT1_ARM_RESET BIT(18) 173 #define SYS_WDT1_FULL_RESET BIT(17) 174 #define SYS_WDT1_SOC_RESET BIT(16) 175 176 #define SYS_CM3_EXT_RESET BIT(6) 177 #define SYS_PCI2_RESET BIT(5) 178 #define SYS_PCI1_RESET BIT(4) 179 #define SYS_DRAM_ECC_RESET BIT(3) 180 #define SYS_FLASH_ABR_RESET BIT(2) 181 #define SYS_EXT_RESET BIT(1) 182 #define SYS_PWR_RESET_FLAG BIT(0) 183 184 #define BIT_WDT_SOC(x) SYS_WDT ## x ## _SOC_RESET 185 #define BIT_WDT_FULL(x) SYS_WDT ## x ## _FULL_RESET 186 #define BIT_WDT_ARM(x) SYS_WDT ## x ## _ARM_RESET 187 #define BIT_WDT_SW(x) SYS_WDT ## x ## _SW_RESET 188 189 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \ 190 if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \ 191 printf("RST: WDT%d ", x); \ 192 if (event_log & BIT_WDT_SOC(x)) { \ 193 printf("SOC "); \ 194 writel(BIT_WDT_SOC(x), event_log_reg); \ 195 } \ 196 if (event_log & BIT_WDT_FULL(x)) { \ 197 printf("FULL "); \ 198 writel(BIT_WDT_FULL(x), event_log_reg); \ 199 } \ 200 if (event_log & BIT_WDT_ARM(x)) { \ 201 printf("ARM "); \ 202 writel(BIT_WDT_ARM(x), event_log_reg); \ 203 } \ 204 if (event_log & BIT_WDT_SW(x)) { \ 205 printf("SW "); \ 206 writel(BIT_WDT_SW(x), event_log_reg); \ 207 } \ 208 printf("\n"); \ 209 } \ 210 (void)(x) 211 212 void aspeed_print_sysrst_info(void) 213 { 214 u32 rest = readl(ASPEED_SYS_RESET_CTRL); 215 u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3); 216 217 if (rest & SYS_PWR_RESET_FLAG) { 218 printf("RST: Power On \n"); 219 writel(rest, ASPEED_SYS_RESET_CTRL); 220 } else { 221 HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3); 222 HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3); 223 HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3); 224 HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3); 225 HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL); 226 HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL); 227 HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL); 228 HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL); 229 230 if (rest & SYS_CM3_EXT_RESET) { 231 printf("RST: SYS_CM3_EXT_RESET \n"); 232 writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL); 233 } 234 235 if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) { 236 printf("PCI RST: "); 237 if (rest & SYS_PCI1_RESET) { 238 printf("#1 "); 239 writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL); 240 } 241 242 if (rest & SYS_PCI2_RESET) { 243 printf("#2 "); 244 writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL); 245 } 246 printf("\n"); 247 } 248 249 if (rest & SYS_DRAM_ECC_RESET) { 250 printf("RST: DRAM_ECC_RESET \n"); 251 writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL); 252 } 253 254 if (rest & SYS_FLASH_ABR_RESET) { 255 printf("RST: SYS_FLASH_ABR_RESET \n"); 256 writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL); 257 } 258 if (rest & SYS_EXT_RESET) { 259 printf("RST: External \n"); 260 writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); 261 } 262 } 263 } 264 265 #define SOC_FW_INIT_DRAM BIT(7) 266 267 void aspeed_print_dram_initializer(void) 268 { 269 if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM) 270 printf("[init by SOC]\n"); 271 else 272 printf("[init by VBIOS]\n"); 273 } 274 275 void aspeed_print_2nd_wdt_mode(void) 276 { 277 /* ABR enable */ 278 if (readl(ASPEED_HW_STRAP2) & BIT(11)) { 279 /* boot from eMMC */ 280 if (readl(ASPEED_HW_STRAP1) & BIT(2)) { 281 printf("eMMC 2nd Boot (ABR): Enable"); 282 printf(", boot partition: %s", \ 283 readl(ASPEED_EMMC_WDT_CTRL) & BIT(4) ? "2" : "1"); 284 printf("\n"); 285 } else { /* boot from SPI */ 286 printf("FMC 2nd Boot (ABR): Enable"); 287 if (readl(ASPEED_HW_STRAP2) & BIT(12)) 288 printf(", Single flash"); 289 else 290 printf(", Dual flashes"); 291 292 printf(", Source: %s", \ 293 readl(ASPEED_FMC_WDT2) & BIT(4) ? "Alternate" : "Primary"); 294 295 if (readl(ASPEED_HW_STRAP2) & GENMASK(15, 13)) 296 printf(", bspi_size: %ld MB", \ 297 BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7)); 298 299 printf("\n"); 300 } 301 } 302 } 303 304 void aspeed_print_fmc_aux_ctrl(void) 305 { 306 307 if (readl(ASPEED_HW_STRAP2) & BIT(22)) { 308 printf("FMC aux control: Enable"); 309 /* gpioY6 : BSPI_ABR */ 310 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(6)) 311 printf(", Force Alt boot"); 312 313 /* gpioY7 : BSPI_WP_N */ 314 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7))) 315 printf(", BSPI_WP: Enable"); 316 317 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)) && \ 318 (readl(ASPEED_HW_STRAP2) & GENMASK(24, 23)) != 0) { 319 printf(", FMC HW CRTM: Enable, size: %ld KB", \ 320 BIT((readl(ASPEED_HW_STRAP2) >> 23) & 0x3) * 128); 321 } 322 323 printf("\n"); 324 } 325 } 326 327 void aspeed_print_spi1_abr_mode(void) 328 { 329 if (readl(ASPEED_HW_STRAP2) & BIT(16)) { 330 printf("SPI1 ABR: Enable"); 331 if(readl(ASPEED_SPI1_BOOT_CTRL) & BIT(6)) 332 printf(", Single flash"); 333 else 334 printf(", Dual flashes"); 335 336 printf(", Source : %s", \ 337 readl(ASPEED_SPI1_BOOT_CTRL) & BIT(4) ? "Alternate" : "Primary"); 338 339 if (readl(ASPEED_SPI1_BOOT_CTRL) & GENMASK(3, 1)) 340 printf(", hspi_size : %ld MB", \ 341 BIT((readl(ASPEED_SPI1_BOOT_CTRL) >> 1) & 0x7)); 342 343 printf("\n"); 344 } 345 346 if (readl(ASPEED_HW_STRAP2) & BIT(17)) { 347 printf("SPI1 select pin: Enable"); 348 /* gpioZ1 : HSPI_ABR */ 349 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9)) 350 printf(", Force Alt boot"); 351 352 printf("\n"); 353 } 354 } 355 356 void aspeed_print_spi1_aux_ctrl(void) 357 { 358 if (readl(ASPEED_HW_STRAP2) & BIT(27)) { 359 printf("SPI1 aux control: Enable"); 360 /* gpioZ1 : HSPI_ABR */ 361 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9)) 362 printf(", Force Alt boot"); 363 364 /* gpioZ2: BSPI_WP_N */ 365 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10))) 366 printf(", HPI_WP: Enable"); 367 368 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)) && \ 369 (readl(ASPEED_HW_STRAP2) & GENMASK(26, 25)) != 0) { 370 printf(", SPI1 HW CRTM: Enable, size: %ld KB", \ 371 BIT((readl(ASPEED_HW_STRAP2) >> 25) & 0x3) * 128); 372 } 373 374 printf("\n"); 375 } 376 } 377 378 void aspeed_print_spi_strap_mode(void) 379 { 380 if(readl(ASPEED_HW_STRAP2) & BIT(10)) 381 printf("SPI: 3/4 byte mode auto detection \n"); 382 } 383 384 void aspeed_print_espi_mode(void) 385 { 386 int espi_mode = 0; 387 int sio_disable = 0; 388 u32 sio_addr = 0x2e; 389 390 if (readl(ASPEED_HW_STRAP2) & BIT(6)) 391 espi_mode = 0; 392 else 393 espi_mode = 1; 394 395 if (readl(ASPEED_HW_STRAP2) & BIT(2)) 396 sio_addr = 0x4e; 397 398 if (readl(ASPEED_HW_STRAP2) & BIT(3)) 399 sio_disable = 1; 400 401 if (espi_mode) 402 printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); 403 else 404 printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); 405 406 if (!sio_disable) 407 printf(": SuperIO-%02x\n", sio_addr); 408 else 409 printf("\n"); 410 } 411 412 void aspeed_print_mac_info(void) 413 { 414 int i; 415 printf("Eth: "); 416 for (i = 0; i < ASPEED_MAC_COUNT; i++) { 417 printf("MAC%d: %s", i, 418 aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI"); 419 if (i != (ASPEED_MAC_COUNT -1)) 420 printf(", "); 421 } 422 printf("\n"); 423 } 424