1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST26x0 DDR3/DDR4 SDRAM controller initialization sequence for FPGA 17 * 18 * Version : 2 19 * Release date: 2019.02.19 20 * 21 * Priority of fix item: 22 * [P1] = critical 23 * [P2] = nice to have 24 * [P3] = minor 25 * 26 * Change List : 27 * V0 |2018.03.28 : 1.[P1] Initial release for simulation 28 * 29 * Optional define variable 30 * 1. ECC Function enable 31 * ASTMMC_DRAM_ECC // define to enable ECC function 32 * ASTMMC_DRAM_ECC_SIZE // define the ECC protected memory size 33 * 2. UART5 message output // 34 * ASTMMC_UART_BASE // select UART port base 35 * 3. DRAM Type 36 * ASTMMC_DDR4_8GX8 // DDR4 (16Gb) 8Gbit X8 stacked part 37 ****************************************************************************** 38 */ 39 40#include <config.h> 41#include <version.h> 42#include <asm/secure.h> 43#include <asm/armv7.h> 44 45#ifdef CONFIG_CPU_ARM1176 46#define ASTMMC_DDR_DDR3 47#else 48#define ASTMMC_READ_TRAINING 49#endif 50 51/****************************************************************************** 52 Calibration Macro Start 53 Usable registers: 54 r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11 55 ******************************************************************************/ 56#define ASTMMC_INIT_VER 0x02 // 8bit verison number 57#define ASTMMC_INIT_DATE 0x20190219 // Release date 58 59/* PATTERN_TABLE, 60 init_delay_timer, 61 check_delay_timer, 62 clear_delay_timer, 63 print_hex_char, 64 print_hex_byte, 65 print_hex_word, 66 print_hex_dword, 67 are for DRAM calibration */ 68 69#define ASTMMC_UART_BASE 0x1E784000 70 71#ifdef CONFIG_DRAM_ECC 72#define ASTMMC_DRAM_ECC 73#define ASTMMC_DRAM_ECC_SIZE CONFIG_DRAM_ECC_SIZE 74#else 75#define ASTMMC_DRAM_ECC_SIZE 0x0 76#endif 77 78#define ASTMMC_REG_MCR10 0x00 79#define ASTMMC_REG_MCR14 0x04 80#define ASTMMC_REG_MCR18 0x08 81#define ASTMMC_REG_MCR1C 0x0C 82#define ASTMMC_REG_MCR20 0x10 83#define ASTMMC_REG_MCR24 0x14 84#define ASTMMC_REG_MCR28 0x18 85#define ASTMMC_REG_MCR2C 0x1C 86#define ASTMMC_REG_RFC 0x20 87 88TIME_TABLE_DDR3: 89 .word 0x02070306 // MCR10 90 .word 0x05021133 // MCR14 91 .word 0x06010200 // MCR18 92 .word 0x00000020 // MCR1C 93 .word 0x00071320 // MCR20 94 .word 0x00000200 // MCR24 95 .word 0x00000000 // MCR28 96 .word 0x00000000 // MCR2C 97 .word 0x17263434 // MCRFC 98TIME_TABLE_DDR4: 99 .word 0x030C0207 // MCR10 100 .word 0x04451133 // MCR14 101 .word 0x0E010200 // MCR18 102 .word 0x00000140 // MCR1C 103 .word 0x03010100 // MCR20 104 .word 0x00000000 // MCR24 105 .word 0x04C00000 // MCR28 106 .word 0x00000050 // MCR2C 107 .word 0x17263434 // MCRFC 108 109PATTERN_TABLE: 110 .word 0xff00ff00 111 .word 0xcc33cc33 112 .word 0xaa55aa55 113 .word 0x88778877 114 .word 0x92cc4d6e // 5 115 .word 0x543d3cde 116 .word 0xf1e843c7 117 .word 0x7c61d253 118 .word 0x00000000 // 8 119 120 .macro init_delay_timer 121 ldr r0, =0x1e782024 // Set Timer3 Reload 122 str r2, [r0] 123 124 ldr r0, =0x1e782034 // Clear Timer3 ISR 125 ldr r1, =0x00000004 126 str r1, [r0] 127 128 ldr r0, =0x1e782030 // Enable Timer3 129 mov r2, #7 130 mov r1, r2, lsl #8 131 str r1, [r0] 132 133 ldr r0, =0x1e782034 // Check ISR for Timer3 timeout 134 .endm 135 136 .macro check_delay_timer 137 ldr r1, [r0] 138 bic r1, r1, #0xFFFFFFFB 139 mov r2, r1, lsr #2 140 cmp r2, #0x01 141 .endm 142 143 .macro clear_delay_timer 144 ldr r0, =0x1e78203C // Disable Timer3 145 mov r2, #0xF 146 mov r1, r2, lsl #8 147 str r1, [r0] 148 149 ldr r0, =0x1e782034 // Clear Timer3 ISR 150 ldr r1, =0x00000004 151 str r1, [r0] 152 .endm 153 154 .macro print_hex_char 155 and r1, r1, #0xF 156 cmp r1, #9 157 addgt r1, r1, #0x37 158 addle r1, r1, #0x30 159 str r1, [r0] 160 .endm 161 162 .macro print_hex_byte 163 ldr r0, =ASTMMC_UART_BASE 164 mov r1, r2, lsr #4 165 print_hex_char 166 mov r1, r2 167 print_hex_char 168 .endm 169 170 .macro print_hex_word 171 ldr r0, =ASTMMC_UART_BASE 172 mov r1, r2, lsr #12 173 print_hex_char 174 mov r1, r2, lsr #8 175 print_hex_char 176 mov r1, r2, lsr #4 177 print_hex_char 178 mov r1, r2 179 print_hex_char 180 .endm 181 182 .macro print_hex_dword 183 ldr r0, =ASTMMC_UART_BASE 184 mov r1, r2, lsr #28 185 print_hex_char 186 mov r1, r2, lsr #24 187 print_hex_char 188 mov r1, r2, lsr #20 189 print_hex_char 190 mov r1, r2, lsr #16 191 print_hex_char 192 mov r1, r2, lsr #12 193 print_hex_char 194 mov r1, r2, lsr #8 195 print_hex_char 196 mov r1, r2, lsr #4 197 print_hex_char 198 mov r1, r2 199 print_hex_char 200 .endm 201 202/****************************************************************************** 203 Calibration Macro End 204 ******************************************************************************/ 205 206.globl lowlevel_init 207lowlevel_init: 208 209#ifndef CONFIG_CPU_ARM1176 210 /* Put secondary core to sleep */ 211 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 212 ands r0, r0, #0x03 @; Mask off, leaving the CPU ID field 213#ifdef CONFIG_ASPEED_NONSECUR_MODE 214 blne secondary_cpu_init 215#else 216 blne relocate 217 @blne wait_for_kickup 218 b init_uart 219#endif 220 221#if 1 222relocate: 223 adrl r0, wait_for_kickup 224 ldr r1, =0x1000f000 // ; r1 = pointer to destination block 225 mov r2, #0x20 // ; r2 = number of words to copy 226wordcopy: 227 ldr r3, [r0], #4 // ; load a word from the source and 228 str r3, [r1], #4 // ; store it to the destination 229 subs r2, r2, #1 // ; decrement the counter 230 bne wordcopy //1 ; ... copy more 231 232 ldr r0, =0x1E6E2180 233 LDR r1, =0x1e784000 234 ldr r4, =0xABBAADDA 235 ldr r3, =0x1E6E2184 236 237 ldr r5, =0x10000000 238 ldr r6, =0x1000f000 239 str r6, [r5] 240 mov lr, r6 241 mov pc, lr 242#endif 243#endif 244 245init_uart: 246 /* save lr */ 247 mov r4, lr 248 249 /*Initialize the Debug UART here*/ 250 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 251 mov r1, #0x83 252 str r1, [r0] 253 254 ldr r0, =(ASTMMC_UART_BASE | 0x00) 255 mov r1, #0x01 256 str r1, [r0] 257 258 ldr r0, =(ASTMMC_UART_BASE | 0x04) 259 mov r1, #0x00 260 str r1, [r0] 261 262 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 263 mov r1, #0x03 264 str r1, [r0] 265 266 ldr r0, =(ASTMMC_UART_BASE | 0x08) 267 mov r1, #0x07 268 str r1, [r0] 269 270init_dram: 271 272/* Test - DRAM initial time */ 273 ldr r0, =0x1e78203c 274 ldr r1, =0x0000F000 275 str r1, [r0] 276 277 ldr r0, =0x1e782044 278 ldr r1, =0xFFFFFFFF 279 str r1, [r0] 280 281 ldr r0, =0x1e782030 282 ldr r1, =0x00003000 283 str r1, [r0] 284/* Test - DRAM initial time */ 285 286 /*Set Scratch register Bit 7 before initialize*/ 287 ldr r0, =0x1e6e2000 288 ldr r1, =0x1688a8a8 289 str r1, [r0] 290 ldr r0, =0x1e6e2010 291 str r1, [r0] 292 293/* ldr r0, =0x1e6e2100 294 ldr r1, [r0] 295 orr r1, r1, #0x80 296 str r1, [r0] 297*/ 298/****************************************************************************** 299 Disable WDT for SPI Address mode detection function 300 ******************************************************************************/ 301 ldr r0, =0x1e620060 302 mov r1, #0 303 str r1, [r0] 304 305 ldr r0, =0x1e620064 306 mov r1, #0 307 str r1, [r0] 308 309 ldr r0, =0x1e78500c 310 mov r1, #0 311 str r1, [r0] 312 ldr r0, =0x1e78504c 313 str r1, [r0] 314 ldr r0, =0x1e78508c 315 str r1, [r0] 316 ldr r0, =0x1e7850cc 317 str r1, [r0] 318 319#ifdef CONFIG_CPU_ARM1176 320 /* Enable AXI_P */ 321/* ldr r0, =0x00000016 322 mrc p15, 0, r1, c15, c2, 4 323 mcr p15, 0, r0, c15, c2, 4 324*/ 325init_arm11: 326 /* Start of ES40004A PLL init */ 327 /* Step 1. Program PLL_config and keep power down */ 328 ldr r0, =0x33000000 329 ldr r1, =0x01000000 330 str r1, [r0] 331 ldr r1, =0x0102001A @ 324 MHz 332 str r1, [r0] 333 334 /* Step 2. Wait 1us for PLL initialization */ 335 ldr r2, =0x00000100 336delay_ES40004A_pll_init: 337 subs r2, r2, #1 338 bne delay_ES40004A_pll_init 339 340 /* Step 3. Program PLL_config to exit Power down */ 341 ldr r1, =0x0002001A 342 str r1, [r0] 343 344 /* Step 4. Check pll_ld = 1?. Read PLL_config, check bit 27. */ 345 ldr r2, =0x08000000 @ bit[27] PLL lock detection 346check_pll_ld: 347 ldr r1, [r0] 348 tst r1, r2 349 beq check_pll_ld 350 351 /* Step 5. Program aclk_div */ 352 ldr r0, =0x33000004 353 ldr r1, =0x00000007 @ CPU/AXI = 8/1 354 str r1, [r0] 355 356 /* Step 6. Program set_pll */ 357 ldr r1, =0x00010007 358 str r1, [r0] 359 /* End of ES40004A PLL init */ 360#endif 361 362 /* skip SDRAM initialization (will be done in C function) */ 363 b platform_exit 364 365platform_exit: 366 /* restore lr */ 367 mov lr, r4 368 369 /* back to arch calling code */ 370 mov pc, lr 371 372secondary_cpu_init: 373#ifdef CONFIG_ASPEED_NONSECUR_MODE 374 mov r6,pc 375 bl start_sec 376#endif 377wait_for_kickup: 378 wfe 379 ldr r2,[r3] 380 cmp r2,r4 381 bne wait_for_kickup 382 383 MOV r2,#'[' 384 STR r2,[r1] 385 MOV r2,#'1' 386 STR r2,[r1] 387 MOV r2,#'C' 388 STR r2,[r1] 389 MOV r2,#'P' 390 STR r2,[r1] 391 MOV r2,#'U' 392 STR r2,[r1] 393 MOV r2,#']' 394 STR r2,[r1] 395 MOV r2,#'\n' 396 STR r2,[r1] 397 MOV r2,#'\r' 398 STR r2,[r1] 399 ldr pc, [r0] 400 ldr pc, [r0] 401 b wait_for_kickup 402