1 #ifndef __ASM_ARM_SYSTEM_H 2 #define __ASM_ARM_SYSTEM_H 3 4 #ifdef CONFIG_ARM64 5 6 /* 7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions 8 */ 9 #define CR_M (1 << 0) /* MMU enable */ 10 #define CR_A (1 << 1) /* Alignment abort enable */ 11 #define CR_C (1 << 2) /* Dcache enable */ 12 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ 13 #define CR_I (1 << 12) /* Icache enable */ 14 #define CR_WXN (1 << 19) /* Write Permision Imply XN */ 15 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 16 17 #define PGTABLE_SIZE (0x10000) 18 19 #ifndef __ASSEMBLY__ 20 21 #define isb() \ 22 ({asm volatile( \ 23 "isb" : : : "memory"); \ 24 }) 25 26 #define wfi() \ 27 ({asm volatile( \ 28 "wfi" : : : "memory"); \ 29 }) 30 31 static inline unsigned int current_el(void) 32 { 33 unsigned int el; 34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); 35 return el >> 2; 36 } 37 38 static inline unsigned int get_sctlr(void) 39 { 40 unsigned int el, val; 41 42 el = current_el(); 43 if (el == 1) 44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); 45 else if (el == 2) 46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); 47 else 48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); 49 50 return val; 51 } 52 53 static inline void set_sctlr(unsigned int val) 54 { 55 unsigned int el; 56 57 el = current_el(); 58 if (el == 1) 59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); 60 else if (el == 2) 61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); 62 else 63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); 64 65 asm volatile("isb"); 66 } 67 68 void __asm_flush_dcache_all(void); 69 void __asm_flush_dcache_range(u64 start, u64 end); 70 void __asm_invalidate_tlb_all(void); 71 void __asm_invalidate_icache_all(void); 72 73 void armv8_switch_to_el2(void); 74 void armv8_switch_to_el1(void); 75 void gic_init(void); 76 void gic_send_sgi(unsigned long sgino); 77 void wait_for_wakeup(void); 78 void smp_kick_all_cpus(void); 79 80 #endif /* __ASSEMBLY__ */ 81 82 #else /* CONFIG_ARM64 */ 83 84 #ifdef __KERNEL__ 85 86 #define CPU_ARCH_UNKNOWN 0 87 #define CPU_ARCH_ARMv3 1 88 #define CPU_ARCH_ARMv4 2 89 #define CPU_ARCH_ARMv4T 3 90 #define CPU_ARCH_ARMv5 4 91 #define CPU_ARCH_ARMv5T 5 92 #define CPU_ARCH_ARMv5TE 6 93 #define CPU_ARCH_ARMv5TEJ 7 94 #define CPU_ARCH_ARMv6 8 95 #define CPU_ARCH_ARMv7 9 96 97 /* 98 * CR1 bits (CP#15 CR1) 99 */ 100 #define CR_M (1 << 0) /* MMU enable */ 101 #define CR_A (1 << 1) /* Alignment abort enable */ 102 #define CR_C (1 << 2) /* Dcache enable */ 103 #define CR_W (1 << 3) /* Write buffer enable */ 104 #define CR_P (1 << 4) /* 32-bit exception handler */ 105 #define CR_D (1 << 5) /* 32-bit data address range */ 106 #define CR_L (1 << 6) /* Implementation defined */ 107 #define CR_B (1 << 7) /* Big endian */ 108 #define CR_S (1 << 8) /* System MMU protection */ 109 #define CR_R (1 << 9) /* ROM MMU protection */ 110 #define CR_F (1 << 10) /* Implementation defined */ 111 #define CR_Z (1 << 11) /* Implementation defined */ 112 #define CR_I (1 << 12) /* Icache enable */ 113 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ 114 #define CR_RR (1 << 14) /* Round Robin cache replacement */ 115 #define CR_L4 (1 << 15) /* LDR pc can set T bit */ 116 #define CR_DT (1 << 16) 117 #define CR_IT (1 << 18) 118 #define CR_ST (1 << 19) 119 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ 120 #define CR_U (1 << 22) /* Unaligned access operation */ 121 #define CR_XP (1 << 23) /* Extended page tables */ 122 #define CR_VE (1 << 24) /* Vectored interrupts */ 123 #define CR_EE (1 << 25) /* Exception (Big) Endian */ 124 #define CR_TRE (1 << 28) /* TEX remap enable */ 125 #define CR_AFE (1 << 29) /* Access flag enable */ 126 #define CR_TE (1 << 30) /* Thumb exception enable */ 127 128 #define PGTABLE_SIZE (4096 * 4) 129 130 /* 131 * This is used to ensure the compiler did actually allocate the register we 132 * asked it for some inline assembly sequences. Apparently we can't trust 133 * the compiler from one version to another so a bit of paranoia won't hurt. 134 * This string is meant to be concatenated with the inline asm string and 135 * will cause compilation to stop on mismatch. 136 * (for details, see gcc PR 15089) 137 */ 138 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" 139 140 #ifndef __ASSEMBLY__ 141 142 #define isb() __asm__ __volatile__ ("" : : : "memory") 143 144 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 145 146 #ifdef __ARM_ARCH_7A__ 147 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 148 #else 149 #define wfi() 150 #endif 151 152 static inline unsigned int get_cr(void) 153 { 154 unsigned int val; 155 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); 156 return val; 157 } 158 159 static inline void set_cr(unsigned int val) 160 { 161 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 162 : : "r" (val) : "cc"); 163 isb(); 164 } 165 166 static inline unsigned int get_dacr(void) 167 { 168 unsigned int val; 169 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); 170 return val; 171 } 172 173 static inline void set_dacr(unsigned int val) 174 { 175 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" 176 : : "r" (val) : "cc"); 177 isb(); 178 } 179 180 /* options available for data cache on each page */ 181 enum dcache_option { 182 DCACHE_OFF = 0x12, 183 DCACHE_WRITETHROUGH = 0x1a, 184 DCACHE_WRITEBACK = 0x1e, 185 }; 186 187 /* Size of an MMU section */ 188 enum { 189 MMU_SECTION_SHIFT = 20, 190 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, 191 }; 192 193 /** 194 * Change the cache settings for a region. 195 * 196 * \param start start address of memory region to change 197 * \param size size of memory region to change 198 * \param option dcache option to select 199 */ 200 void mmu_set_region_dcache_behaviour(u32 start, int size, 201 enum dcache_option option); 202 203 /** 204 * Register an update to the page tables, and flush the TLB 205 * 206 * \param start start address of update in page table 207 * \param stop stop address of update in page table 208 */ 209 void mmu_page_table_flush(unsigned long start, unsigned long stop); 210 211 #endif /* __ASSEMBLY__ */ 212 213 #define arch_align_stack(x) (x) 214 215 #endif /* __KERNEL__ */ 216 217 #endif /* CONFIG_ARM64 */ 218 219 #endif 220