193bc2193SAneesh V /* 293bc2193SAneesh V * (C) Copyright 2010 393bc2193SAneesh V * Texas Instruments, <www.ti.com> 493bc2193SAneesh V * Aneesh V <aneesh@ti.com> 593bc2193SAneesh V * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 793bc2193SAneesh V */ 893bc2193SAneesh V #ifndef _PL310_H_ 993bc2193SAneesh V #define _PL310_H_ 1093bc2193SAneesh V 1193bc2193SAneesh V #include <linux/types.h> 1293bc2193SAneesh V 1393bc2193SAneesh V /* Register bit fields */ 1493bc2193SAneesh V #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) 156d73c234SFabio Estevam #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) 166d73c234SFabio Estevam #define L2X0_STNDBY_MODE_EN (1 << 0) 176d73c234SFabio Estevam #define L2X0_CTRL_EN 1 1893bc2193SAneesh V 19*b4ed9f86SFabio Estevam #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) 20*b4ed9f86SFabio Estevam 2193bc2193SAneesh V struct pl310_regs { 2293bc2193SAneesh V u32 pl310_cache_id; 2393bc2193SAneesh V u32 pl310_cache_type; 2493bc2193SAneesh V u32 pad1[62]; 2593bc2193SAneesh V u32 pl310_ctrl; 2693bc2193SAneesh V u32 pl310_aux_ctrl; 2793bc2193SAneesh V u32 pl310_tag_latency_ctrl; 2893bc2193SAneesh V u32 pl310_data_latency_ctrl; 2993bc2193SAneesh V u32 pad2[60]; 3093bc2193SAneesh V u32 pl310_event_cnt_ctrl; 3193bc2193SAneesh V u32 pl310_event_cnt1_cfg; 3293bc2193SAneesh V u32 pl310_event_cnt0_cfg; 3393bc2193SAneesh V u32 pl310_event_cnt1_val; 3493bc2193SAneesh V u32 pl310_event_cnt0_val; 3593bc2193SAneesh V u32 pl310_intr_mask; 3693bc2193SAneesh V u32 pl310_masked_intr_stat; 3793bc2193SAneesh V u32 pl310_raw_intr_stat; 3893bc2193SAneesh V u32 pl310_intr_clear; 3993bc2193SAneesh V u32 pad3[323]; 4093bc2193SAneesh V u32 pl310_cache_sync; 4193bc2193SAneesh V u32 pad4[15]; 4293bc2193SAneesh V u32 pl310_inv_line_pa; 4393bc2193SAneesh V u32 pad5[2]; 4493bc2193SAneesh V u32 pl310_inv_way; 4593bc2193SAneesh V u32 pad6[12]; 4693bc2193SAneesh V u32 pl310_clean_line_pa; 4793bc2193SAneesh V u32 pad7[1]; 4893bc2193SAneesh V u32 pl310_clean_line_idx; 4993bc2193SAneesh V u32 pl310_clean_way; 5093bc2193SAneesh V u32 pad8[12]; 5193bc2193SAneesh V u32 pl310_clean_inv_line_pa; 5293bc2193SAneesh V u32 pad9[1]; 5393bc2193SAneesh V u32 pl310_clean_inv_line_idx; 5493bc2193SAneesh V u32 pl310_clean_inv_way; 556d73c234SFabio Estevam u32 pad10[64]; 566d73c234SFabio Estevam u32 pl310_lockdown_dbase; 576d73c234SFabio Estevam u32 pl310_lockdown_ibase; 586d73c234SFabio Estevam u32 pad11[190]; 596d73c234SFabio Estevam u32 pl310_addr_filter_start; 606d73c234SFabio Estevam u32 pl310_addr_filter_end; 616d73c234SFabio Estevam u32 pad12[190]; 626d73c234SFabio Estevam u32 pl310_test_operation; 636d73c234SFabio Estevam u32 pad13[3]; 646d73c234SFabio Estevam u32 pl310_line_data; 656d73c234SFabio Estevam u32 pad14[7]; 666d73c234SFabio Estevam u32 pl310_line_tag; 676d73c234SFabio Estevam u32 pad15[3]; 686d73c234SFabio Estevam u32 pl310_debug_ctrl; 696d73c234SFabio Estevam u32 pad16[7]; 706d73c234SFabio Estevam u32 pl310_prefetch_ctrl; 716d73c234SFabio Estevam u32 pad17[7]; 726d73c234SFabio Estevam u32 pl310_power_ctrl; 7393bc2193SAneesh V }; 7493bc2193SAneesh V 7593bc2193SAneesh V void pl310_inval_all(void); 7693bc2193SAneesh V void pl310_clean_inval_all(void); 7793bc2193SAneesh V void pl310_inval_range(u32 start, u32 end); 7893bc2193SAneesh V void pl310_clean_inval_range(u32 start, u32 end); 7993bc2193SAneesh V 8093bc2193SAneesh V #endif 81