1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2dc89ad14STom Warren /* 3dc89ad14STom Warren * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 4dc89ad14STom Warren */ 5dc89ad14STom Warren 6dc89ad14STom Warren #ifndef _TEGRA30_H_ 7dc89ad14STom Warren #define _TEGRA30_H_ 8dc89ad14STom Warren 98c33ba7bSMarcel Ziswiler #define NV_PA_MC_BASE 0x7000F000 10dc89ad14STom Warren #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ 11dc89ad14STom Warren 12dc89ad14STom Warren #include <asm/arch-tegra/tegra.h> 13dc89ad14STom Warren 147ae18f37SLucas Stach #define TEGRA_USB1_BASE 0x7D000000 157ae18f37SLucas Stach 16dc89ad14STom Warren #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ 17dc89ad14STom Warren 18f29f086aSTom Warren #define MAX_NUM_CPU 4 19f29f086aSTom Warren 20dc89ad14STom Warren #endif /* TEGRA30_H */ 21