1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 28c33ba7bSMarcel Ziswiler /* 38c33ba7bSMarcel Ziswiler * (C) Copyright 2014 48c33ba7bSMarcel Ziswiler * NVIDIA Corporation <www.nvidia.com> 58c33ba7bSMarcel Ziswiler */ 68c33ba7bSMarcel Ziswiler 78c33ba7bSMarcel Ziswiler #ifndef _TEGRA30_MC_H_ 88c33ba7bSMarcel Ziswiler #define _TEGRA30_MC_H_ 98c33ba7bSMarcel Ziswiler 108c33ba7bSMarcel Ziswiler /** 118c33ba7bSMarcel Ziswiler * Defines the memory controller registers we need/care about 128c33ba7bSMarcel Ziswiler */ 138c33ba7bSMarcel Ziswiler struct mc_ctlr { 148c33ba7bSMarcel Ziswiler u32 reserved0[4]; /* offset 0x00 - 0x0C */ 158c33ba7bSMarcel Ziswiler u32 mc_smmu_config; /* offset 0x10 */ 168c33ba7bSMarcel Ziswiler u32 mc_smmu_tlb_config; /* offset 0x14 */ 178c33ba7bSMarcel Ziswiler u32 mc_smmu_ptc_config; /* offset 0x18 */ 188c33ba7bSMarcel Ziswiler u32 mc_smmu_ptb_asid; /* offset 0x1C */ 198c33ba7bSMarcel Ziswiler u32 mc_smmu_ptb_data; /* offset 0x20 */ 208c33ba7bSMarcel Ziswiler u32 reserved1[3]; /* offset 0x24 - 0x2C */ 218c33ba7bSMarcel Ziswiler u32 mc_smmu_tlb_flush; /* offset 0x30 */ 228c33ba7bSMarcel Ziswiler u32 mc_smmu_ptc_flush; /* offset 0x34 */ 238c33ba7bSMarcel Ziswiler u32 mc_smmu_asid_security; /* offset 0x38 */ 248c33ba7bSMarcel Ziswiler u32 reserved2[5]; /* offset 0x3C - 0x4C */ 258c33ba7bSMarcel Ziswiler u32 mc_emem_cfg; /* offset 0x50 */ 268c33ba7bSMarcel Ziswiler u32 mc_emem_adr_cfg; /* offset 0x54 */ 278c33ba7bSMarcel Ziswiler u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 288c33ba7bSMarcel Ziswiler u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 298c33ba7bSMarcel Ziswiler u32 reserved3[12]; /* offset 0x60 - 0x8C */ 308c33ba7bSMarcel Ziswiler u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 318c33ba7bSMarcel Ziswiler u32 reserved4[338]; /* offset 0x100 - 0x644 */ 328c33ba7bSMarcel Ziswiler u32 mc_video_protect_bom; /* offset 0x648 */ 338c33ba7bSMarcel Ziswiler u32 mc_video_protect_size_mb; /* offset 0x64c */ 348c33ba7bSMarcel Ziswiler u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 358c33ba7bSMarcel Ziswiler }; 368c33ba7bSMarcel Ziswiler 378c33ba7bSMarcel Ziswiler #endif /* _TEGRA30_MC_H_ */ 38