1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c43f6c8STom Warren /* 36c43f6c8STom Warren * (C) Copyright 2013-2015 46c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 56c43f6c8STom Warren */ 66c43f6c8STom Warren 76c43f6c8STom Warren #ifndef _TEGRA210_SYSCTR_H_ 86c43f6c8STom Warren #define _TEGRA210_SYSCTR_H_ 96c43f6c8STom Warren 106c43f6c8STom Warren struct sysctr_ctlr { 116c43f6c8STom Warren u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 126c43f6c8STom Warren u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 136c43f6c8STom Warren u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 146c43f6c8STom Warren u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 156c43f6c8STom Warren u32 reserved1[4]; /* 0x10 - 0x1C */ 166c43f6c8STom Warren u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 176c43f6c8STom Warren u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 186c43f6c8STom Warren u32 reserved2[1002]; /* 0x28 - 0xFCC */ 196c43f6c8STom Warren u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 206c43f6c8STom Warren }; 216c43f6c8STom Warren 226c43f6c8STom Warren #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 236c43f6c8STom Warren #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 246c43f6c8STom Warren 256c43f6c8STom Warren #endif /* _TEGRA210_SYSCTR_H_ */ 26