1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2150c2493STom Warren /* 3150c2493STom Warren * (C) Copyright 2010,2011 4150c2493STom Warren * NVIDIA Corporation <www.nvidia.com> 5150c2493STom Warren */ 6150c2493STom Warren 7150c2493STom Warren #ifndef _TEGRA20_H_ 8150c2493STom Warren #define _TEGRA20_H_ 9150c2493STom Warren 10150c2493STom Warren #define NV_PA_SDRAM_BASE 0x00000000 118c33ba7bSMarcel Ziswiler #define NV_PA_MC_BASE 0x7000F000 12150c2493STom Warren 13150c2493STom Warren #include <asm/arch-tegra/tegra.h> 14150c2493STom Warren 15150c2493STom Warren #define TEGRA_USB1_BASE 0xC5000000 16150c2493STom Warren 17150c2493STom Warren #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ 18150c2493STom Warren 19f29f086aSTom Warren #define MAX_NUM_CPU 2 20f29f086aSTom Warren 21150c2493STom Warren #endif /* TEGRA20_H */ 22