1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 200a2749dSAllen Martin /* 300a2749dSAllen Martin * Copyright (c) 2011, Google Inc. All rights reserved. 400a2749dSAllen Martin * Portions Copyright 2011-2012 NVIDIA Corporation 500a2749dSAllen Martin */ 600a2749dSAllen Martin 7150c2493STom Warren #ifndef _TEGRA20_GPIO_H_ 8150c2493STom Warren #define _TEGRA20_GPIO_H_ 900a2749dSAllen Martin 1000a2749dSAllen Martin /* 1100a2749dSAllen Martin * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, 1200a2749dSAllen Martin * each with 8 GPIOs. 1300a2749dSAllen Martin */ 1400a2749dSAllen Martin #define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ 1500a2749dSAllen Martin #define TEGRA_GPIO_BANKS 7 /* number of banks */ 16150c2493STom Warren 17150c2493STom Warren #include <asm/arch-tegra/gpio.h> 1800a2749dSAllen Martin 1900a2749dSAllen Martin /* GPIO Controller registers for a single bank */ 2000a2749dSAllen Martin struct gpio_ctlr_bank { 2100a2749dSAllen Martin uint gpio_config[TEGRA_GPIO_PORTS]; 2200a2749dSAllen Martin uint gpio_dir_out[TEGRA_GPIO_PORTS]; 2300a2749dSAllen Martin uint gpio_out[TEGRA_GPIO_PORTS]; 2400a2749dSAllen Martin uint gpio_in[TEGRA_GPIO_PORTS]; 2500a2749dSAllen Martin uint gpio_int_status[TEGRA_GPIO_PORTS]; 2600a2749dSAllen Martin uint gpio_int_enable[TEGRA_GPIO_PORTS]; 2700a2749dSAllen Martin uint gpio_int_level[TEGRA_GPIO_PORTS]; 2800a2749dSAllen Martin uint gpio_int_clear[TEGRA_GPIO_PORTS]; 2900a2749dSAllen Martin }; 3000a2749dSAllen Martin 3100a2749dSAllen Martin struct gpio_ctlr { 3200a2749dSAllen Martin struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; 3300a2749dSAllen Martin }; 3400a2749dSAllen Martin 35150c2493STom Warren #endif /* TEGRA20_GPIO_H_ */ 36