1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2999c6bafSTom Warren /* 3999c6bafSTom Warren * (C) Copyright 2013 4999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 5999c6bafSTom Warren */ 6999c6bafSTom Warren 7999c6bafSTom Warren #ifndef _TEGRA124_SYSCTR_H_ 8999c6bafSTom Warren #define _TEGRA124_SYSCTR_H_ 9999c6bafSTom Warren 10999c6bafSTom Warren struct sysctr_ctlr { 11999c6bafSTom Warren u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 12999c6bafSTom Warren u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 13999c6bafSTom Warren u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 14999c6bafSTom Warren u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 15999c6bafSTom Warren u32 reserved1[4]; /* 0x10 - 0x1C */ 16999c6bafSTom Warren u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 17999c6bafSTom Warren u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 18999c6bafSTom Warren u32 reserved2[1002]; /* 0x28 - 0xFCC */ 19999c6bafSTom Warren u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 20999c6bafSTom Warren }; 21999c6bafSTom Warren 22999c6bafSTom Warren #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 23999c6bafSTom Warren #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 24999c6bafSTom Warren 25999c6bafSTom Warren #endif /* _TEGRA124_SYSCTR_H_ */ 26