1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 292369844SChen-Yu Tsai /* 392369844SChen-Yu Tsai * (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org> 492369844SChen-Yu Tsai */ 592369844SChen-Yu Tsai 692369844SChen-Yu Tsai #ifndef _SUNXI_TZPC_H 792369844SChen-Yu Tsai #define _SUNXI_TZPC_H 892369844SChen-Yu Tsai 992369844SChen-Yu Tsai #ifndef __ASSEMBLY__ 1092369844SChen-Yu Tsai struct sunxi_tzpc { 1192369844SChen-Yu Tsai u32 r0size; /* 0x00 Size of secure RAM region */ 1292369844SChen-Yu Tsai u32 decport0_status; /* 0x04 Status of decode protection port 0 */ 1392369844SChen-Yu Tsai u32 decport0_set; /* 0x08 Set decode protection port 0 */ 1492369844SChen-Yu Tsai u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ 155823664fSChen-Yu Tsai /* For A80 and later SoCs */ 165823664fSChen-Yu Tsai u32 decport1_status; /* 0x10 Status of decode protection port 1 */ 175823664fSChen-Yu Tsai u32 decport1_set; /* 0x14 Set decode protection port 1 */ 185823664fSChen-Yu Tsai u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ 195823664fSChen-Yu Tsai u32 decport2_status; /* 0x1c Status of decode protection port 2 */ 205823664fSChen-Yu Tsai u32 decport2_set; /* 0x20 Set decode protection port 2 */ 215823664fSChen-Yu Tsai u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ 2292369844SChen-Yu Tsai }; 2392369844SChen-Yu Tsai #endif 2492369844SChen-Yu Tsai 255823664fSChen-Yu Tsai #define SUN6I_TZPC_DECPORT0_RTC (1 << 1) 265823664fSChen-Yu Tsai 275823664fSChen-Yu Tsai #define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe 285823664fSChen-Yu Tsai #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff 295823664fSChen-Yu Tsai #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f 3092369844SChen-Yu Tsai 3192369844SChen-Yu Tsai void tzpc_init(void); 3292369844SChen-Yu Tsai 3392369844SChen-Yu Tsai #endif /* _SUNXI_TZPC_H */ 34