xref: /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/dram.h (revision 5665f50e81fc76932307fa2351357517af31fefa)
1286c3c3aSIan Campbell /*
2286c3c3aSIan Campbell  * (C) Copyright 2007-2012
3286c3c3aSIan Campbell  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4286c3c3aSIan Campbell  * Berg Xing <bergxing@allwinnertech.com>
5286c3c3aSIan Campbell  * Tom Cubie <tangliang@allwinnertech.com>
6286c3c3aSIan Campbell  *
7286c3c3aSIan Campbell  * Sunxi platform dram register definition.
8286c3c3aSIan Campbell  *
9286c3c3aSIan Campbell  * SPDX-License-Identifier:	GPL-2.0+
10286c3c3aSIan Campbell  */
11286c3c3aSIan Campbell 
12286c3c3aSIan Campbell #ifndef _SUNXI_DRAM_H
13286c3c3aSIan Campbell #define _SUNXI_DRAM_H
14286c3c3aSIan Campbell 
1507f4fe7dSHans de Goede #include <asm/io.h>
16286c3c3aSIan Campbell #include <linux/types.h>
17286c3c3aSIan Campbell 
18bec72c79SHans de Goede /* dram regs definition */
199a07eb0bSHans de Goede #if defined(CONFIG_MACH_SUN6I)
209a07eb0bSHans de Goede #include <asm/arch/dram_sun6i.h>
219a07eb0bSHans de Goede #else
22bec72c79SHans de Goede #include <asm/arch/dram_sun4i.h>
239a07eb0bSHans de Goede #endif
24286c3c3aSIan Campbell 
25*5665f50eSHans de Goede #define MCTL_MEM_FILL_MATCH_COUNT 64
26*5665f50eSHans de Goede 
27286c3c3aSIan Campbell unsigned long sunxi_dram_init(void);
28286c3c3aSIan Campbell 
2907f4fe7dSHans de Goede /*
3007f4fe7dSHans de Goede  * Wait up to 1s for value to be set in given part of reg.
3107f4fe7dSHans de Goede  */
3207f4fe7dSHans de Goede static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
3307f4fe7dSHans de Goede {
3407f4fe7dSHans de Goede 	unsigned long tmo = timer_get_us() + 1000000;
3507f4fe7dSHans de Goede 
3607f4fe7dSHans de Goede 	while ((readl(reg) & mask) != val) {
3707f4fe7dSHans de Goede 		if (timer_get_us() > tmo)
3807f4fe7dSHans de Goede 			panic("Timeout initialising DRAM\n");
3907f4fe7dSHans de Goede 	}
4007f4fe7dSHans de Goede }
4107f4fe7dSHans de Goede 
42*5665f50eSHans de Goede /*
43*5665f50eSHans de Goede  * Fill beginning of DRAM with "random" data for mctl_mem_matches()
44*5665f50eSHans de Goede  */
45*5665f50eSHans de Goede static inline void mctl_mem_fill(void)
46*5665f50eSHans de Goede {
47*5665f50eSHans de Goede 	int i;
48*5665f50eSHans de Goede 
49*5665f50eSHans de Goede 	for (i = 0; i < MCTL_MEM_FILL_MATCH_COUNT; i++)
50*5665f50eSHans de Goede 		writel(0xaa55aa55 + i, CONFIG_SYS_SDRAM_BASE + i * 4);
51*5665f50eSHans de Goede }
52*5665f50eSHans de Goede 
53*5665f50eSHans de Goede /*
54*5665f50eSHans de Goede  * Test if memory at offset offset matches memory at begin of DRAM
55*5665f50eSHans de Goede  */
56*5665f50eSHans de Goede static inline bool mctl_mem_matches(u32 offset)
57*5665f50eSHans de Goede {
58*5665f50eSHans de Goede 	int i, matches = 0;
59*5665f50eSHans de Goede 
60*5665f50eSHans de Goede 	for (i = 0; i < MCTL_MEM_FILL_MATCH_COUNT; i++) {
61*5665f50eSHans de Goede 		if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
62*5665f50eSHans de Goede 		    readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
63*5665f50eSHans de Goede 			matches++;
64*5665f50eSHans de Goede 	}
65*5665f50eSHans de Goede 
66*5665f50eSHans de Goede 	return matches == MCTL_MEM_FILL_MATCH_COUNT;
67*5665f50eSHans de Goede }
68*5665f50eSHans de Goede 
69286c3c3aSIan Campbell #endif /* _SUNXI_DRAM_H */
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