1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a19e735dSRoy Spliet /* 3a19e735dSRoy Spliet * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> 4a19e735dSRoy Spliet */ 5a19e735dSRoy Spliet 6a19e735dSRoy Spliet #ifndef _SUNXI_DMA_SUN4I_H 7a19e735dSRoy Spliet #define _SUNXI_DMA_SUN4I_H 8a19e735dSRoy Spliet 9a19e735dSRoy Spliet struct sunxi_dma_cfg 10a19e735dSRoy Spliet { 11a19e735dSRoy Spliet u32 ctl; /* 0x00 Control */ 12a19e735dSRoy Spliet u32 src_addr; /* 0x04 Source address */ 13a19e735dSRoy Spliet u32 dst_addr; /* 0x08 Destination address */ 14a19e735dSRoy Spliet u32 bc; /* 0x0C Byte counter */ 15a19e735dSRoy Spliet u32 res0[2]; 16a19e735dSRoy Spliet u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ 17a19e735dSRoy Spliet u32 res1; 18a19e735dSRoy Spliet }; 19a19e735dSRoy Spliet 20a19e735dSRoy Spliet struct sunxi_dma 21a19e735dSRoy Spliet { 22a19e735dSRoy Spliet u32 irq_en; /* 0x000 IRQ enable */ 23a19e735dSRoy Spliet u32 irq_pend; /* 0x004 IRQ pending */ 24a19e735dSRoy Spliet u32 auto_gate; /* 0x008 auto gating */ 25a19e735dSRoy Spliet u32 res0[61]; 26a19e735dSRoy Spliet struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ 27a19e735dSRoy Spliet u32 res1[64]; 28a19e735dSRoy Spliet struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ 29a19e735dSRoy Spliet }; 30a19e735dSRoy Spliet 31a19e735dSRoy Spliet enum ddma_drq_type { 32a19e735dSRoy Spliet DDMA_DST_DRQ_SRAM = 0, 33a19e735dSRoy Spliet DDMA_SRC_DRQ_SRAM = 0, 34a19e735dSRoy Spliet DDMA_DST_DRQ_SDRAM = 1, 35a19e735dSRoy Spliet DDMA_SRC_DRQ_SDRAM = 1, 36a19e735dSRoy Spliet DDMA_DST_DRQ_PATA = 2, 37a19e735dSRoy Spliet DDMA_SRC_DRQ_PATA = 2, 38a19e735dSRoy Spliet DDMA_DST_DRQ_NAND = 3, 39a19e735dSRoy Spliet DDMA_SRC_DRQ_NAND = 3, 40a19e735dSRoy Spliet DDMA_DST_DRQ_USB0 = 4, 41a19e735dSRoy Spliet DDMA_SRC_DRQ_USB0 = 4, 42a19e735dSRoy Spliet DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, 43a19e735dSRoy Spliet DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, 44a19e735dSRoy Spliet DDMA_DST_DRQ_SPI1_TX = 8, 45a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI1_RX = 9, 46a19e735dSRoy Spliet DDMA_DST_DRQ_SECURITY_SYS_TX = 10, 47a19e735dSRoy Spliet DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, 48a19e735dSRoy Spliet DDMA_DST_DRQ_TCON0 = 14, 49a19e735dSRoy Spliet DDMA_DST_DRQ_TCON1 = 15, 50a19e735dSRoy Spliet DDMA_DST_DRQ_MSC = 23, 51a19e735dSRoy Spliet DDMA_SRC_DRQ_MSC = 23, 52a19e735dSRoy Spliet DDMA_DST_DRQ_SPI0_TX = 26, 53a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI0_RX = 27, 54a19e735dSRoy Spliet DDMA_DST_DRQ_SPI2_TX = 28, 55a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI2_RX = 29, 56a19e735dSRoy Spliet DDMA_DST_DRQ_SPI3_TX = 30, 57a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI3_RX = 31, 58a19e735dSRoy Spliet }; 59a19e735dSRoy Spliet 60a19e735dSRoy Spliet #define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) 61a19e735dSRoy Spliet #define SUNXI_DMA_CTL_MODE_IO (1 << 5) 62a19e735dSRoy Spliet #define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) 63a19e735dSRoy Spliet #define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) 64a19e735dSRoy Spliet #define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) 65a19e735dSRoy Spliet #define SUNXI_DMA_CTL_TRIGGER (1 << 31) 66a19e735dSRoy Spliet 67a19e735dSRoy Spliet #endif /* _SUNXI_DMA_SUN4I_H */ 68