1 /* 2 * Copyright (c) 2015 Google, Inc 3 * 4 * Copyright 2014 Rockchip Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 10 #define _ASM_ARCH_RK3288_SDRAM_H__ 11 12 enum { 13 DDR3 = 3, 14 LPDDR3 = 6, 15 UNUSED = 0xFF, 16 }; 17 18 struct rk3288_sdram_channel { 19 u8 rank; 20 u8 col; 21 u8 bk; 22 u8 bw; 23 u8 dbw; 24 u8 row_3_4; 25 u8 cs0_row; 26 u8 cs1_row; 27 #if CONFIG_IS_ENABLED(OF_PLATDATA) 28 /* 29 * For of-platdata, which would otherwise convert this into two 30 * byte-swapped integers. With a size of 9 bytes, this struct will 31 * appear in of-platdata as a byte array. 32 * 33 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 34 */ 35 u8 dummy; 36 #endif 37 }; 38 39 struct rk3288_sdram_pctl_timing { 40 u32 togcnt1u; 41 u32 tinit; 42 u32 trsth; 43 u32 togcnt100n; 44 u32 trefi; 45 u32 tmrd; 46 u32 trfc; 47 u32 trp; 48 u32 trtw; 49 u32 tal; 50 u32 tcl; 51 u32 tcwl; 52 u32 tras; 53 u32 trc; 54 u32 trcd; 55 u32 trrd; 56 u32 trtp; 57 u32 twr; 58 u32 twtr; 59 u32 texsr; 60 u32 txp; 61 u32 txpdll; 62 u32 tzqcs; 63 u32 tzqcsi; 64 u32 tdqs; 65 u32 tcksre; 66 u32 tcksrx; 67 u32 tcke; 68 u32 tmod; 69 u32 trstl; 70 u32 tzqcl; 71 u32 tmrr; 72 u32 tckesr; 73 u32 tdpd; 74 }; 75 check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 76 77 struct rk3288_sdram_phy_timing { 78 u32 dtpr0; 79 u32 dtpr1; 80 u32 dtpr2; 81 u32 mr[4]; 82 }; 83 84 struct rk3288_base_params { 85 u32 noc_timing; 86 u32 noc_activate; 87 u32 ddrconfig; 88 u32 ddr_freq; 89 u32 dramtype; 90 u32 stride; 91 u32 odt; 92 }; 93 94 #endif 95