15ff093abSSimon Glass /* 25ff093abSSimon Glass * Copyright (c) 2015 Google, Inc 35ff093abSSimon Glass * 45ff093abSSimon Glass * Copyright 2014 Rockchip Inc. 55ff093abSSimon Glass * 65ff093abSSimon Glass * SPDX-License-Identifier: GPL-2.0 75ff093abSSimon Glass */ 85ff093abSSimon Glass 95ff093abSSimon Glass #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 105ff093abSSimon Glass #define _ASM_ARCH_RK3288_SDRAM_H__ 115ff093abSSimon Glass 125ff093abSSimon Glass enum { 135ff093abSSimon Glass DDR3 = 3, 145ff093abSSimon Glass LPDDR3 = 6, 155ff093abSSimon Glass UNUSED = 0xFF, 165ff093abSSimon Glass }; 175ff093abSSimon Glass 185ff093abSSimon Glass struct rk3288_sdram_channel { 195ff093abSSimon Glass u8 rank; 205ff093abSSimon Glass u8 col; 215ff093abSSimon Glass u8 bk; 225ff093abSSimon Glass u8 bw; 235ff093abSSimon Glass u8 dbw; 245ff093abSSimon Glass u8 row_3_4; 255ff093abSSimon Glass u8 cs0_row; 265ff093abSSimon Glass u8 cs1_row; 27*ce26e8a1SXu Ziyuan #if CONFIG_IS_ENABLED(OF_PLATDATA) 289ca7e672SSimon Glass /* 299ca7e672SSimon Glass * For of-platdata, which would otherwise convert this into two 309ca7e672SSimon Glass * byte-swapped integers. With a size of 9 bytes, this struct will 319ca7e672SSimon Glass * appear in of-platdata as a byte array. 32*ce26e8a1SXu Ziyuan * 33*ce26e8a1SXu Ziyuan * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 349ca7e672SSimon Glass */ 359ca7e672SSimon Glass u8 dummy; 36*ce26e8a1SXu Ziyuan #endif 375ff093abSSimon Glass }; 385ff093abSSimon Glass 395ff093abSSimon Glass struct rk3288_sdram_pctl_timing { 405ff093abSSimon Glass u32 togcnt1u; 415ff093abSSimon Glass u32 tinit; 425ff093abSSimon Glass u32 trsth; 435ff093abSSimon Glass u32 togcnt100n; 445ff093abSSimon Glass u32 trefi; 455ff093abSSimon Glass u32 tmrd; 465ff093abSSimon Glass u32 trfc; 475ff093abSSimon Glass u32 trp; 485ff093abSSimon Glass u32 trtw; 495ff093abSSimon Glass u32 tal; 505ff093abSSimon Glass u32 tcl; 515ff093abSSimon Glass u32 tcwl; 525ff093abSSimon Glass u32 tras; 535ff093abSSimon Glass u32 trc; 545ff093abSSimon Glass u32 trcd; 555ff093abSSimon Glass u32 trrd; 565ff093abSSimon Glass u32 trtp; 575ff093abSSimon Glass u32 twr; 585ff093abSSimon Glass u32 twtr; 595ff093abSSimon Glass u32 texsr; 605ff093abSSimon Glass u32 txp; 615ff093abSSimon Glass u32 txpdll; 625ff093abSSimon Glass u32 tzqcs; 635ff093abSSimon Glass u32 tzqcsi; 645ff093abSSimon Glass u32 tdqs; 655ff093abSSimon Glass u32 tcksre; 665ff093abSSimon Glass u32 tcksrx; 675ff093abSSimon Glass u32 tcke; 685ff093abSSimon Glass u32 tmod; 695ff093abSSimon Glass u32 trstl; 705ff093abSSimon Glass u32 tzqcl; 715ff093abSSimon Glass u32 tmrr; 725ff093abSSimon Glass u32 tckesr; 735ff093abSSimon Glass u32 tdpd; 745ff093abSSimon Glass }; 755ff093abSSimon Glass check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 765ff093abSSimon Glass 775ff093abSSimon Glass struct rk3288_sdram_phy_timing { 785ff093abSSimon Glass u32 dtpr0; 795ff093abSSimon Glass u32 dtpr1; 805ff093abSSimon Glass u32 dtpr2; 815ff093abSSimon Glass u32 mr[4]; 825ff093abSSimon Glass }; 835ff093abSSimon Glass 845ff093abSSimon Glass struct rk3288_base_params { 855ff093abSSimon Glass u32 noc_timing; 865ff093abSSimon Glass u32 noc_activate; 875ff093abSSimon Glass u32 ddrconfig; 885ff093abSSimon Glass u32 ddr_freq; 895ff093abSSimon Glass u32 dramtype; 905ff093abSSimon Glass u32 stride; 915ff093abSSimon Glass u32 odt; 925ff093abSSimon Glass }; 935ff093abSSimon Glass 945ff093abSSimon Glass #endif 95