1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 234374699SSimon Glass /* 334374699SSimon Glass * (C) Copyright 2012 SAMSUNG Electronics 434374699SSimon Glass * Jaehoon Chung <jh80.chung@samsung.com> 534374699SSimon Glass */ 634374699SSimon Glass 734374699SSimon Glass #ifndef __ASM_ARCH_I2C_H 834374699SSimon Glass #define __ASM_ARCH_I2C_H 934374699SSimon Glass 1034374699SSimon Glass struct i2c_regs { 1134374699SSimon Glass u32 con; 1234374699SSimon Glass u32 clkdiv; 1334374699SSimon Glass u32 mrxaddr; 1434374699SSimon Glass u32 mrxraddr; 1534374699SSimon Glass u32 mtxcnt; 1634374699SSimon Glass u32 mrxcnt; 1734374699SSimon Glass u32 ien; 1834374699SSimon Glass u32 ipd; 1934374699SSimon Glass u32 fcnt; 2034374699SSimon Glass u32 reserved0[0x37]; 2134374699SSimon Glass u32 txdata[8]; 2234374699SSimon Glass u32 reserved1[0x38]; 2334374699SSimon Glass u32 rxdata[8]; 2434374699SSimon Glass }; 2534374699SSimon Glass 2634374699SSimon Glass /* Control register */ 2734374699SSimon Glass #define I2C_CON_EN (1 << 0) 2834374699SSimon Glass #define I2C_CON_MOD(mod) ((mod) << 1) 2934374699SSimon Glass #define I2C_MODE_TX 0x00 3034374699SSimon Glass #define I2C_MODE_TRX 0x01 3134374699SSimon Glass #define I2C_MODE_RX 0x02 3234374699SSimon Glass #define I2C_MODE_RRX 0x03 3334374699SSimon Glass #define I2C_CON_MASK (3 << 1) 3434374699SSimon Glass 3534374699SSimon Glass #define I2C_CON_START (1 << 3) 3634374699SSimon Glass #define I2C_CON_STOP (1 << 4) 3734374699SSimon Glass #define I2C_CON_LASTACK (1 << 5) 3834374699SSimon Glass #define I2C_CON_ACTACK (1 << 6) 3934374699SSimon Glass 4034374699SSimon Glass /* Clock dividor register */ 4134374699SSimon Glass #define I2C_CLKDIV_VAL(divl, divh) \ 4234374699SSimon Glass (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) 4334374699SSimon Glass 4434374699SSimon Glass /* the slave address accessed for master rx mode */ 4534374699SSimon Glass #define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) 4634374699SSimon Glass 4734374699SSimon Glass /* the slave register address accessed for master rx mode */ 4834374699SSimon Glass #define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) 4934374699SSimon Glass 5034374699SSimon Glass /* interrupt enable register */ 5134374699SSimon Glass #define I2C_BTFIEN (1 << 0) 5234374699SSimon Glass #define I2C_BRFIEN (1 << 1) 5334374699SSimon Glass #define I2C_MBTFIEN (1 << 2) 5434374699SSimon Glass #define I2C_MBRFIEN (1 << 3) 5534374699SSimon Glass #define I2C_STARTIEN (1 << 4) 5634374699SSimon Glass #define I2C_STOPIEN (1 << 5) 5734374699SSimon Glass #define I2C_NAKRCVIEN (1 << 6) 5834374699SSimon Glass 5934374699SSimon Glass /* interrupt pending register */ 6034374699SSimon Glass #define I2C_BTFIPD (1 << 0) 6134374699SSimon Glass #define I2C_BRFIPD (1 << 1) 6234374699SSimon Glass #define I2C_MBTFIPD (1 << 2) 6334374699SSimon Glass #define I2C_MBRFIPD (1 << 3) 6434374699SSimon Glass #define I2C_STARTIPD (1 << 4) 6534374699SSimon Glass #define I2C_STOPIPD (1 << 5) 6634374699SSimon Glass #define I2C_NAKRCVIPD (1 << 6) 6734374699SSimon Glass #define I2C_IPD_ALL_CLEAN 0x7f 6834374699SSimon Glass 6934374699SSimon Glass #endif 70