1*ae485b54SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0+ */ 2*ae485b54SManivannan Sadhasivam /* 3*ae485b54SManivannan Sadhasivam * Actions Semi S900 Register Definitions 4*ae485b54SManivannan Sadhasivam * 5*ae485b54SManivannan Sadhasivam * Copyright (C) 2015 Actions Semi Co., Ltd. 6*ae485b54SManivannan Sadhasivam * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7*ae485b54SManivannan Sadhasivam * 8*ae485b54SManivannan Sadhasivam */ 9*ae485b54SManivannan Sadhasivam 10*ae485b54SManivannan Sadhasivam #ifndef _OWL_REGS_S900_H_ 11*ae485b54SManivannan Sadhasivam #define _OWL_REGS_S900_H_ 12*ae485b54SManivannan Sadhasivam 13*ae485b54SManivannan Sadhasivam /* CMU registers */ 14*ae485b54SManivannan Sadhasivam #define CMU_COREPLL (0x0000) 15*ae485b54SManivannan Sadhasivam #define CMU_DEVPLL (0x0004) 16*ae485b54SManivannan Sadhasivam #define CMU_DDRPLL (0x0008) 17*ae485b54SManivannan Sadhasivam #define CMU_NANDPLL (0x000C) 18*ae485b54SManivannan Sadhasivam #define CMU_DISPLAYPLL (0x0010) 19*ae485b54SManivannan Sadhasivam #define CMU_AUDIOPLL (0x0014) 20*ae485b54SManivannan Sadhasivam #define CMU_TVOUTPLL (0x0018) 21*ae485b54SManivannan Sadhasivam #define CMU_BUSCLK (0x001C) 22*ae485b54SManivannan Sadhasivam #define CMU_SENSORCLK (0x0020) 23*ae485b54SManivannan Sadhasivam #define CMU_LCDCLK (0x0024) 24*ae485b54SManivannan Sadhasivam #define CMU_DSICLK (0x0028) 25*ae485b54SManivannan Sadhasivam #define CMU_CSICLK (0x002C) 26*ae485b54SManivannan Sadhasivam #define CMU_DECLK (0x0030) 27*ae485b54SManivannan Sadhasivam #define CMU_BISPCLK (0x0034) 28*ae485b54SManivannan Sadhasivam #define CMU_IMXCLK (0x0038) 29*ae485b54SManivannan Sadhasivam #define CMU_HDECLK (0x003C) 30*ae485b54SManivannan Sadhasivam #define CMU_VDECLK (0x0040) 31*ae485b54SManivannan Sadhasivam #define CMU_VCECLK (0x0044) 32*ae485b54SManivannan Sadhasivam #define CMU_NANDCCLK (0x004C) 33*ae485b54SManivannan Sadhasivam #define CMU_SD0CLK (0x0050) 34*ae485b54SManivannan Sadhasivam #define CMU_SD1CLK (0x0054) 35*ae485b54SManivannan Sadhasivam #define CMU_SD2CLK (0x0058) 36*ae485b54SManivannan Sadhasivam #define CMU_UART0CLK (0x005C) 37*ae485b54SManivannan Sadhasivam #define CMU_UART1CLK (0x0060) 38*ae485b54SManivannan Sadhasivam #define CMU_UART2CLK (0x0064) 39*ae485b54SManivannan Sadhasivam #define CMU_PWM0CLK (0x0070) 40*ae485b54SManivannan Sadhasivam #define CMU_PWM1CLK (0x0074) 41*ae485b54SManivannan Sadhasivam #define CMU_PWM2CLK (0x0078) 42*ae485b54SManivannan Sadhasivam #define CMU_PWM3CLK (0x007C) 43*ae485b54SManivannan Sadhasivam #define CMU_USBPLL (0x0080) 44*ae485b54SManivannan Sadhasivam #define CMU_ASSISTPLL (0x0084) 45*ae485b54SManivannan Sadhasivam #define CMU_EDPCLK (0x0088) 46*ae485b54SManivannan Sadhasivam #define CMU_GPU3DCLK (0x0090) 47*ae485b54SManivannan Sadhasivam #define CMU_CORECTL (0x009C) 48*ae485b54SManivannan Sadhasivam #define CMU_DEVCLKEN0 (0x00A0) 49*ae485b54SManivannan Sadhasivam #define CMU_DEVCLKEN1 (0x00A4) 50*ae485b54SManivannan Sadhasivam #define CMU_DEVRST0 (0x00A8) 51*ae485b54SManivannan Sadhasivam #define CMU_DEVRST1 (0x00AC) 52*ae485b54SManivannan Sadhasivam #define CMU_UART3CLK (0x00B0) 53*ae485b54SManivannan Sadhasivam #define CMU_UART4CLK (0x00B4) 54*ae485b54SManivannan Sadhasivam #define CMU_UART5CLK (0x00B8) 55*ae485b54SManivannan Sadhasivam #define CMU_UART6CLK (0x00BC) 56*ae485b54SManivannan Sadhasivam #define CMU_TLSCLK (0x00C0) 57*ae485b54SManivannan Sadhasivam #define CMU_SD3CLK (0x00C4) 58*ae485b54SManivannan Sadhasivam #define CMU_PWM4CLK (0x00C8) 59*ae485b54SManivannan Sadhasivam #define CMU_PWM5CLK (0x00CC) 60*ae485b54SManivannan Sadhasivam #define CMU_ANALOGDEBUG (0x00D4) 61*ae485b54SManivannan Sadhasivam #define CMU_TVOUTPLLDEBUG0 (0x00EC) 62*ae485b54SManivannan Sadhasivam #define CMU_TVOUTPLLDEBUG1 (0x00FC) 63*ae485b54SManivannan Sadhasivam 64*ae485b54SManivannan Sadhasivam #endif 65