1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _OMAP5_H_ 13 #define _OMAP5_H_ 14 15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16 #include <asm/types.h> 17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18 19 /* 20 * L4 Peripherals - L4 Wakeup and L4 Core now 21 */ 22 #define OMAP54XX_L4_CORE_BASE 0x4A000000 23 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 24 #define OMAP54XX_L4_PER_BASE 0x48000000 25 26 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 27 #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF 28 #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START 29 #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END 30 31 /* CONTROL ID CODE */ 32 #define CONTROL_CORE_ID_CODE 0x4A002204 33 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 34 35 #ifdef CONFIG_DRA7XX 36 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE 37 #else 38 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE 39 #endif 40 41 /* To be verified */ 42 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 43 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 44 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 45 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 46 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 47 48 /* UART */ 49 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 50 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 51 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 52 53 /* General Purpose Timers */ 54 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 55 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 56 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 57 58 /* Watchdog Timer2 - MPU watchdog */ 59 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 60 61 /* GPMC */ 62 #define OMAP54XX_GPMC_BASE 0x50000000 63 64 /* 65 * Hardware Register Details 66 */ 67 68 /* Watchdog Timer */ 69 #define WD_UNLOCK1 0xAAAA 70 #define WD_UNLOCK2 0x5555 71 72 /* GP Timer */ 73 #define TCLR_ST (0x1 << 0) 74 #define TCLR_AR (0x1 << 1) 75 #define TCLR_PRE (0x1 << 5) 76 77 /* Control Module */ 78 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 79 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 80 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 81 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 82 83 /* LPDDR2 IO regs */ 84 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 85 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 86 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 87 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 88 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 89 90 /* CONTROL_EFUSE_2 */ 91 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 92 93 #define SDCARD_BIAS_PWRDNZ (1 << 27) 94 #define SDCARD_PWRDNZ (1 << 26) 95 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 96 #define SDCARD_PBIASLITE_VMODE (1 << 21) 97 98 #ifndef __ASSEMBLY__ 99 100 struct s32ktimer { 101 unsigned char res[0x10]; 102 unsigned int s32k_cr; /* 0x10 */ 103 }; 104 105 #define DEVICE_TYPE_SHIFT 0x6 106 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 107 #define DEVICE_GP 0x3 108 109 /* Output impedance control */ 110 #define ds_120_ohm 0x0 111 #define ds_60_ohm 0x1 112 #define ds_45_ohm 0x2 113 #define ds_30_ohm 0x3 114 #define ds_mask 0x3 115 116 /* Slew rate control */ 117 #define sc_slow 0x0 118 #define sc_medium 0x1 119 #define sc_fast 0x2 120 #define sc_na 0x3 121 #define sc_mask 0x3 122 123 /* Target capacitance control */ 124 #define lb_5_12_pf 0x0 125 #define lb_12_25_pf 0x1 126 #define lb_25_50_pf 0x2 127 #define lb_50_80_pf 0x3 128 #define lb_mask 0x3 129 130 #define usb_i_mask 0x7 131 132 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 133 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 134 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 135 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 136 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 137 138 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 139 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 140 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 141 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 142 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 143 144 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 145 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 146 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 147 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 148 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 149 150 #define EFUSE_1 0x45145100 151 #define EFUSE_2 0x45145100 152 #define EFUSE_3 0x45145100 153 #define EFUSE_4 0x45145100 154 #endif /* __ASSEMBLY__ */ 155 156 #ifdef CONFIG_DRA7XX 157 #define NON_SECURE_SRAM_START 0x40300000 158 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 159 #else 160 #define NON_SECURE_SRAM_START 0x40300000 161 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 162 #endif 163 #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START 164 165 /* base address for indirect vectors (internal boot mode) */ 166 #define SRAM_ROM_VECT_BASE 0x4031F000 167 168 /* CONTROL_SRCOMP_XXX_SIDE */ 169 #define OVERRIDE_XS_SHIFT 30 170 #define OVERRIDE_XS_MASK (1 << 30) 171 #define SRCODE_READ_XS_SHIFT 12 172 #define SRCODE_READ_XS_MASK (0xff << 12) 173 #define PWRDWN_XS_SHIFT 11 174 #define PWRDWN_XS_MASK (1 << 11) 175 #define DIVIDE_FACTOR_XS_SHIFT 4 176 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 177 #define MULTIPLY_FACTOR_XS_SHIFT 1 178 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 179 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 180 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 181 182 /* ABB settings */ 183 #define OMAP_ABB_SETTLING_TIME 50 184 #define OMAP_ABB_CLOCK_CYCLES 16 185 186 /* ABB tranxdone mask */ 187 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 188 189 /* ABB efuse masks */ 190 #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) 191 #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) 192 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) 193 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) 194 195 /* IO Delay module defines */ 196 #define CFG_IO_DELAY_BASE 0x4844A000 197 #define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) 198 199 /* CPSW IO Delay registers*/ 200 #define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) 201 #define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) 202 #define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) 203 #define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) 204 #define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) 205 #define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) 206 #define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) 207 #define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) 208 #define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) 209 #define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) 210 211 #define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA 212 #define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB 213 #define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 214 #define CFG_IO_DELAY_LOCK_MASK 0x400 215 216 #ifndef __ASSEMBLY__ 217 struct srcomp_params { 218 s8 divide_factor; 219 s8 multiply_factor; 220 }; 221 222 struct ctrl_ioregs { 223 u32 ctrl_ddrch; 224 u32 ctrl_lpddr2ch; 225 u32 ctrl_ddr3ch; 226 u32 ctrl_ddrio_0; 227 u32 ctrl_ddrio_1; 228 u32 ctrl_ddrio_2; 229 u32 ctrl_emif_sdram_config_ext; 230 u32 ctrl_ddr_ctrl_ext_0; 231 }; 232 233 struct io_delay { 234 u32 addr; 235 u32 dly; 236 }; 237 #endif /* __ASSEMBLY__ */ 238 #endif 239