1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ASM_ARCH_MXC_MX51_H__ 24 #define __ASM_ARCH_MXC_MX51_H__ 25 26 /* 27 * IRAM 28 */ 29 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 30 #define IRAM_SIZE 0x00020000 /* 128 KB */ 31 /* 32 * Graphics Memory of GPU 33 */ 34 #define GPU_BASE_ADDR 0x20000000 35 #define GPU_CTRL_BASE_ADDR 0x30000000 36 #define IPU_CTRL_BASE_ADDR 0x40000000 37 /* 38 * Debug 39 */ 40 #define DEBUG_BASE_ADDR 0x60000000 41 #define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) 42 #define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) 43 #define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) 44 #define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) 45 #define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) 46 #define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) 47 #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) 48 #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) 49 50 /* 51 * SPBA global module enabled #0 52 */ 53 #define SPBA0_BASE_ADDR 0x70000000 54 55 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 56 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 57 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) 58 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 59 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 60 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 61 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 62 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 63 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 64 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 65 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 66 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 67 68 /* 69 * AIPS 1 70 */ 71 #define AIPS1_BASE_ADDR 0x73F00000 72 73 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 74 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 75 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 76 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 77 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 78 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 79 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 80 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 81 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 82 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 83 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 84 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 85 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 86 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 87 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 88 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) 89 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) 90 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 91 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 92 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 93 94 /* 95 * AIPS 2 96 */ 97 #define AIPS2_BASE_ADDR 0x83F00000 98 99 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 100 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 101 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 102 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 103 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 104 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 105 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 106 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 107 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 108 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 109 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 110 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 111 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 112 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 113 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 114 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 115 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 116 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 117 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 118 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 119 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 120 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 121 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 122 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 123 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 124 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 125 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 126 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 127 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 128 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 129 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 130 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 131 132 #define TZIC_BASE_ADDR 0x8FFFC000 133 134 /* 135 * Memory regions and CS 136 */ 137 #define CSD0_BASE_ADDR 0x90000000 138 #define CSD1_BASE_ADDR 0xA0000000 139 #define CS0_BASE_ADDR 0xB0000000 140 #define CS1_BASE_ADDR 0xB8000000 141 #define CS2_BASE_ADDR 0xC0000000 142 #define CS3_BASE_ADDR 0xC8000000 143 #define CS4_BASE_ADDR 0xCC000000 144 #define CS5_BASE_ADDR 0xCE000000 145 146 /* 147 * NFC 148 */ 149 #define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ 150 151 /*! 152 * Number of GPIO port as defined in the IC Spec 153 */ 154 #define GPIO_PORT_NUM 4 155 /*! 156 * Number of GPIO pins per port 157 */ 158 #define GPIO_NUM_PIN 32 159 160 #define IIM_SREV 0x24 161 #define ROM_SI_REV 0x48 162 163 #define NFC_BUF_SIZE 0x1000 164 165 /* M4IF */ 166 #define M4IF_FBPM0 0x40 167 #define M4IF_FIDBP 0x48 168 169 /* Assuming 24MHz input clock with doubler ON */ 170 /* MFI PDF */ 171 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 172 #define DP_MFD_850 (48 - 1) 173 #define DP_MFN_850 41 174 175 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 176 #define DP_MFD_800 (3 - 1) 177 #define DP_MFN_800 1 178 179 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 180 #define DP_MFD_700 (24 - 1) 181 #define DP_MFN_700 7 182 183 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 184 #define DP_MFD_665 (96 - 1) 185 #define DP_MFN_665 89 186 187 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 188 #define DP_MFD_532 (24 - 1) 189 #define DP_MFN_532 13 190 191 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 192 #define DP_MFD_400 (3 - 1) 193 #define DP_MFN_400 1 194 195 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 196 #define DP_MFD_216 (4 - 1) 197 #define DP_MFN_216 3 198 199 #define CHIP_REV_1_0 0x10 200 #define CHIP_REV_1_1 0x11 201 #define CHIP_REV_2_0 0x20 202 #define CHIP_REV_2_5 0x25 203 #define CHIP_REV_3_0 0x30 204 205 #define BOARD_REV_1_0 0x0 206 #define BOARD_REV_2_0 0x1 207 208 #define IMX_IIM_BASE (IIM_BASE_ADDR) 209 210 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 211 #include <asm/types.h> 212 213 extern void imx_get_mac_from_fuse(unsigned char *mac); 214 215 #define __REG(x) (*((volatile u32 *)(x))) 216 #define __REG16(x) (*((volatile u16 *)(x))) 217 #define __REG8(x) (*((volatile u8 *)(x))) 218 219 struct clkctl { 220 u32 ccr; 221 u32 ccdr; 222 u32 csr; 223 u32 ccsr; 224 u32 cacrr; 225 u32 cbcdr; 226 u32 cbcmr; 227 u32 cscmr1; 228 u32 cscmr2; 229 u32 cscdr1; 230 u32 cs1cdr; 231 u32 cs2cdr; 232 u32 cdcdr; 233 u32 chsccdr; 234 u32 cscdr2; 235 u32 cscdr3; 236 u32 cscdr4; 237 u32 cwdr; 238 u32 cdhipr; 239 u32 cdcr; 240 u32 ctor; 241 u32 clpcr; 242 u32 cisr; 243 u32 cimr; 244 u32 ccosr; 245 u32 cgpr; 246 u32 ccgr0; 247 u32 ccgr1; 248 u32 ccgr2; 249 u32 ccgr3; 250 u32 ccgr4; 251 u32 ccgr5; 252 u32 ccgr6; 253 u32 cmeor; 254 }; 255 256 /* WEIM registers */ 257 struct weim { 258 u32 csgcr1; 259 u32 csgcr2; 260 u32 csrcr1; 261 u32 csrcr2; 262 u32 cswcr1; 263 u32 cswcr2; 264 }; 265 266 /* GPIO Registers */ 267 struct gpio_regs { 268 u32 gpio_dr; 269 u32 gpio_dir; 270 u32 gpio_psr; 271 }; 272 273 /* System Reset Controller (SRC) */ 274 struct src { 275 u32 scr; 276 u32 sbmr; 277 u32 srsr; 278 u32 reserved1[2]; 279 u32 sisr; 280 u32 simr; 281 }; 282 283 struct iim_regs { 284 u32 stat; 285 u32 statm; 286 u32 err; 287 u32 emask; 288 u32 fctl; 289 u32 ua; 290 u32 la; 291 u32 sdat; 292 u32 prev; 293 u32 srev; 294 u32 preg_p; 295 u32 scs0; 296 u32 scs1; 297 u32 scs2; 298 u32 scs3; 299 u32 res0[0x1f1]; 300 struct fuse_bank { 301 u32 fuse_regs[0x20]; 302 u32 fuse_rsvd[0xe0]; 303 } bank[4]; 304 }; 305 306 struct fuse_bank1_regs { 307 u32 fuse0_8[9]; 308 u32 mac_addr[6]; 309 u32 fuse15_31[0x11]; 310 }; 311 312 #endif /* __ASSEMBLER__*/ 313 314 #endif /* __ASM_ARCH_MXC_MX51_H__ */ 315