1*485bba39SNeil Armstrong /* SPDX-License-Identifier: GPL-2.0+ */ 2*485bba39SNeil Armstrong /* 3*485bba39SNeil Armstrong * Copyright (C) 2018 BayLibre, SAS 4*485bba39SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5*485bba39SNeil Armstrong */ 6*485bba39SNeil Armstrong 7*485bba39SNeil Armstrong #ifndef __AXG_H__ 8*485bba39SNeil Armstrong #define __AXG_H__ 9*485bba39SNeil Armstrong 10*485bba39SNeil Armstrong #define AXG_AOBUS_BASE 0xff800000 11*485bba39SNeil Armstrong #define AXG_PERIPHS_BASE 0xff634400 12*485bba39SNeil Armstrong #define AXG_HIU_BASE 0xff63c000 13*485bba39SNeil Armstrong #define AXG_ETH_BASE 0xff3f0000 14*485bba39SNeil Armstrong 15*485bba39SNeil Armstrong /* Always-On Peripherals registers */ 16*485bba39SNeil Armstrong #define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) 17*485bba39SNeil Armstrong 18*485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) 19*485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) 20*485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) 21*485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) 22*485bba39SNeil Armstrong 23*485bba39SNeil Armstrong #define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 24*485bba39SNeil Armstrong #define AXG_AO_MEM_SIZE_SHIFT 16 25*485bba39SNeil Armstrong #define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 26*485bba39SNeil Armstrong #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 27*485bba39SNeil Armstrong #define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF 28*485bba39SNeil Armstrong 29*485bba39SNeil Armstrong /* Peripherals registers */ 30*485bba39SNeil Armstrong #define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) 31*485bba39SNeil Armstrong 32*485bba39SNeil Armstrong #define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) 33*485bba39SNeil Armstrong #define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) 34*485bba39SNeil Armstrong 35*485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) 36*485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) 37*485bba39SNeil Armstrong #define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 38*485bba39SNeil Armstrong #define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 39*485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) 40*485bba39SNeil Armstrong #define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) 41*485bba39SNeil Armstrong #define AXG_ETH_REG_0_CLK_EN BIT(12) 42*485bba39SNeil Armstrong 43*485bba39SNeil Armstrong /* HIU registers */ 44*485bba39SNeil Armstrong #define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) 45*485bba39SNeil Armstrong 46*485bba39SNeil Armstrong #define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) 47*485bba39SNeil Armstrong 48*485bba39SNeil Armstrong /* Ethernet memory power domain */ 49*485bba39SNeil Armstrong #define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 50*485bba39SNeil Armstrong 51*485bba39SNeil Armstrong #endif /* __AXG_H__ */ 52