1 /* 2 * Copyright 2014, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_ 8 #define _ASM_ARMV7_LS102XA_CONFIG_ 9 10 #define OCRAM_BASE_ADDR 0x10000000 11 #define OCRAM_SIZE 0x00010000 12 #define OCRAM_BASE_S_ADDR 0x10010000 13 #define OCRAM_S_SIZE 0x00010000 14 15 #define CONFIG_SYS_IMMR 0x01000000 16 #define CONFIG_SYS_DCSRBAR 0x20000000 17 18 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 19 20 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 21 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 22 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 23 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 24 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 26 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 27 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 28 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 29 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 30 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 31 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 32 #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 33 #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) 34 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 35 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 36 #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) 37 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 38 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 39 40 #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 41 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 42 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 43 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 44 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 45 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 46 47 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 48 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 49 50 #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 51 52 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 53 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 54 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 55 56 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 57 58 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 59 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 60 61 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 62 63 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 64 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 65 66 #define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL 67 #define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL 68 #define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL 69 #define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL 70 #define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ 71 /* 72 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) 73 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. 74 */ 75 #define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ 76 CONFIG_SYS_PCIE1_VIRT_ADDR) 77 #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ 78 CONFIG_SYS_PCIE2_VIRT_ADDR) 79 80 /* SATA */ 81 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 82 #define CONFIG_BOARD_LATE_INIT 83 #define CONFIG_SCSI 84 #define CONFIG_LIBATA 85 #define CONFIG_SCSI_AHCI 86 #define CONFIG_SCSI_AHCI_PLAT 87 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 88 #define CONFIG_SYS_SCSI_MAX_LUN 1 89 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 90 CONFIG_SYS_SCSI_MAX_LUN) 91 #define CONFIG_DOS_PARTITION 92 #define CONFIG_SYS_FSL_ERRATUM_A008407 93 94 #ifdef CONFIG_DDR_SPD 95 #define CONFIG_SYS_FSL_DDR_BE 96 #define CONFIG_VERY_BIG_RAM 97 #ifdef CONFIG_SYS_FSL_DDR4 98 #define CONFIG_SYS_FSL_DDRC_GEN4 99 #else 100 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 101 #endif 102 #define CONFIG_SYS_FSL_DDR 103 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 104 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 105 #endif 106 107 #define CONFIG_SYS_FSL_IFC_BE 108 #define CONFIG_SYS_FSL_ESDHC_BE 109 #define CONFIG_SYS_FSL_WDOG_BE 110 #define CONFIG_SYS_FSL_DSPI_BE 111 #define CONFIG_SYS_FSL_QSPI_BE 112 #define CONFIG_SYS_FSL_DCU_BE 113 #define CONFIG_SYS_FSL_SEC_MON_LE 114 #define CONFIG_SYS_FSL_SEC_LE 115 #define CONFIG_SYS_FSL_SFP_VER_3_2 116 #define CONFIG_SYS_FSL_SFP_BE 117 #define CONFIG_SYS_FSL_SRK_LE 118 119 #define DCU_LAYER_MAX_NUM 16 120 121 #define CONFIG_SYS_FSL_SRDS_1 122 123 #ifdef CONFIG_LS102XA 124 #define CONFIG_MAX_CPUS 2 125 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 126 #define CONFIG_NUM_DDR_CONTROLLERS 1 127 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 128 #define CONFIG_SYS_FSL_SEC_COMPAT 5 129 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 130 #define CONFIG_SYS_FSL_ERRATUM_A008378 131 #define CONFIG_SYS_FSL_ERRATUM_A009663 132 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 133 #else 134 #error SoC not defined 135 #endif 136 137 #define FSL_IFC_COMPAT "fsl,ifc" 138 #define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" 139 #define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" 140 141 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 142