1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2412ae53aSAlbert ARIBAUD \(3ADEV\) /* 3412ae53aSAlbert ARIBAUD \(3ADEV\) * LPC32xx MUX interface 4412ae53aSAlbert ARIBAUD \(3ADEV\) * 5412ae53aSAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2015 DENX Software Engineering GmbH 6412ae53aSAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 7412ae53aSAlbert ARIBAUD \(3ADEV\) */ 8412ae53aSAlbert ARIBAUD \(3ADEV\) 9412ae53aSAlbert ARIBAUD \(3ADEV\) /** 10412ae53aSAlbert ARIBAUD \(3ADEV\) * MUX register map for LPC32xx 11412ae53aSAlbert ARIBAUD \(3ADEV\) */ 12412ae53aSAlbert ARIBAUD \(3ADEV\) 13412ae53aSAlbert ARIBAUD \(3ADEV\) struct mux_regs { 14d75b532aSSylvain Lemieux u32 reserved1[10]; 15d75b532aSSylvain Lemieux u32 p2_mux_set; 16d75b532aSSylvain Lemieux u32 p2_mux_clr; 17d75b532aSSylvain Lemieux u32 p2_mux_state; 18d75b532aSSylvain Lemieux u32 reserved2[51]; 19412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_set; 20412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_clr; 21412ae53aSAlbert ARIBAUD \(3ADEV\) u32 p_mux_state; 22d75b532aSSylvain Lemieux u32 reserved3; 23d75b532aSSylvain Lemieux u32 p3_mux_set; 24d75b532aSSylvain Lemieux u32 p3_mux_clr; 25d75b532aSSylvain Lemieux u32 p3_mux_state; 26d75b532aSSylvain Lemieux u32 reserved4; 27d75b532aSSylvain Lemieux u32 p0_mux_set; 28d75b532aSSylvain Lemieux u32 p0_mux_clr; 29d75b532aSSylvain Lemieux u32 p0_mux_state; 30d75b532aSSylvain Lemieux u32 reserved5; 31d75b532aSSylvain Lemieux u32 p1_mux_set; 32d75b532aSSylvain Lemieux u32 p1_mux_clr; 33d75b532aSSylvain Lemieux u32 p1_mux_state; 34412ae53aSAlbert ARIBAUD \(3ADEV\) }; 35