1dcf846d5STENART Antoine /* 2dcf846d5STENART Antoine * hardware_ti816x.h 3dcf846d5STENART Antoine * 4dcf846d5STENART Antoine * TI816x hardware specific header 5dcf846d5STENART Antoine * 6dcf846d5STENART Antoine * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 7dcf846d5STENART Antoine * Antoine Tenart, <atenart@adeneo-embedded.com> 8dcf846d5STENART Antoine * Based on TI-PSP-04.00.02.14 9dcf846d5STENART Antoine * 10dcf846d5STENART Antoine * This program is free software; you can redistribute it and/or 11dcf846d5STENART Antoine * modify it under the terms of the GNU General Public License as 12dcf846d5STENART Antoine * published by the Free Software Foundation; either version 2 of 13dcf846d5STENART Antoine * the License, or (at your option) any later version. 14dcf846d5STENART Antoine * 15dcf846d5STENART Antoine * This program is distributed in the hope that it will be useful, 16dcf846d5STENART Antoine * but WITHOUT ANY WARRANTY; without even the implied warranty of 17dcf846d5STENART Antoine * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 18dcf846d5STENART Antoine * GNU General Public License for more details. 19dcf846d5STENART Antoine */ 20dcf846d5STENART Antoine 21dcf846d5STENART Antoine #ifndef __AM33XX_HARDWARE_TI816X_H 22dcf846d5STENART Antoine #define __AM33XX_HARDWARE_TI816X_H 23dcf846d5STENART Antoine 24dcf846d5STENART Antoine /* UART */ 25dcf846d5STENART Antoine #define UART0_BASE 0x48020000 26dcf846d5STENART Antoine #define UART1_BASE 0x48022000 27dcf846d5STENART Antoine #define UART2_BASE 0x48024000 28dcf846d5STENART Antoine 29dcf846d5STENART Antoine /* Watchdog Timer */ 30dcf846d5STENART Antoine #define WDT_BASE 0x480C2000 31dcf846d5STENART Antoine 32dcf846d5STENART Antoine /* Control Module Base Address */ 33dcf846d5STENART Antoine #define CTRL_BASE 0x48140000 34*de820365STom Rini #define CTRL_DEVICE_BASE 0x48140600 35dcf846d5STENART Antoine 36dcf846d5STENART Antoine /* PRCM Base Address */ 37dcf846d5STENART Antoine #define PRCM_BASE 0x48180000 38dcf846d5STENART Antoine 39dcf846d5STENART Antoine #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 40dcf846d5STENART Antoine #define PRM_RSTST (PRM_RSTCTRL + 8) 41dcf846d5STENART Antoine 42dcf846d5STENART Antoine /* VTP Base address */ 43dcf846d5STENART Antoine #define VTP0_CTRL_ADDR 0x48198358 44dcf846d5STENART Antoine #define VTP1_CTRL_ADDR 0x4819A358 45dcf846d5STENART Antoine 46dcf846d5STENART Antoine /* DDR Base address */ 47dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR 0x48198000 48dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR 0x481980C8 49dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR2 0x4819A000 50dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR2 0x4819A0C8 51dcf846d5STENART Antoine #define DDR_DATA_REGS_NR 4 52dcf846d5STENART Antoine 53dcf846d5STENART Antoine 54dcf846d5STENART Antoine #define DDRPHY_0_CONFIG_BASE 0x48198000 55dcf846d5STENART Antoine #define DDRPHY_1_CONFIG_BASE 0x4819A000 56dcf846d5STENART Antoine #define DDRPHY_CONFIG_BASE ((emif == 0) ? \ 57dcf846d5STENART Antoine DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) 58dcf846d5STENART Antoine 59dcf846d5STENART Antoine /* RTC base address */ 60dcf846d5STENART Antoine #define RTC_BASE 0x480C0000 61dcf846d5STENART Antoine 62dcf846d5STENART Antoine #endif /* __AM33XX_HARDWARE_TI816X_H */ 63