1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b43c17cbSMatt Porter /* 3b43c17cbSMatt Porter * hardware_ti814x.h 4b43c17cbSMatt Porter * 5b43c17cbSMatt Porter * TI814x hardware specific header 6b43c17cbSMatt Porter * 7b43c17cbSMatt Porter * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 8b43c17cbSMatt Porter */ 9b43c17cbSMatt Porter 10b43c17cbSMatt Porter #ifndef __AM33XX_HARDWARE_TI814X_H 11b43c17cbSMatt Porter #define __AM33XX_HARDWARE_TI814X_H 12b43c17cbSMatt Porter 138b029f22SMatt Porter /* Module base addresses */ 148b029f22SMatt Porter 158b029f22SMatt Porter /* UART Base Address */ 168b029f22SMatt Porter #define UART0_BASE 0x48020000 178b029f22SMatt Porter 188b029f22SMatt Porter /* Watchdog Timer */ 198b029f22SMatt Porter #define WDT_BASE 0x481C7000 208b029f22SMatt Porter 218b029f22SMatt Porter /* Control Module Base Address */ 228b029f22SMatt Porter #define CTRL_BASE 0x48140000 23035d5639SMatt Porter #define CTRL_DEVICE_BASE 0x48140600 248b029f22SMatt Porter 258b029f22SMatt Porter /* PRCM Base Address */ 268b029f22SMatt Porter #define PRCM_BASE 0x48180000 27c06e498aSLokesh Vutla #define CM_PER 0x44E00000 28c06e498aSLokesh Vutla #define CM_WKUP 0x44E00400 29c06e498aSLokesh Vutla 30c06e498aSLokesh Vutla #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 31c06e498aSLokesh Vutla #define PRM_RSTST (PRM_RSTCTRL + 8) 328b029f22SMatt Porter 338b029f22SMatt Porter /* PLL Subsystem Base Address */ 348b029f22SMatt Porter #define PLL_SUBSYS_BASE 0x481C5000 358b029f22SMatt Porter 36b43c17cbSMatt Porter /* VTP Base address */ 37b43c17cbSMatt Porter #define VTP0_CTRL_ADDR 0x48140E0C 38dcf846d5STENART Antoine #define VTP1_CTRL_ADDR 0x48140E10 39b43c17cbSMatt Porter 40b43c17cbSMatt Porter /* DDR Base address */ 41b43c17cbSMatt Porter #define DDR_PHY_CMD_ADDR 0x47C0C400 42b43c17cbSMatt Porter #define DDR_PHY_DATA_ADDR 0x47C0C4C8 43dcf846d5STENART Antoine #define DDR_PHY_CMD_ADDR2 0x47C0C800 44dcf846d5STENART Antoine #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 45b43c17cbSMatt Porter #define DDR_DATA_REGS_NR 4 46b43c17cbSMatt Porter 47dcf846d5STENART Antoine #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 48dcf846d5STENART Antoine #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 49dcf846d5STENART Antoine 508b029f22SMatt Porter /* CPSW Config space */ 518b029f22SMatt Porter #define CPSW_MDIO_BASE 0x4A100800 528b029f22SMatt Porter 538b029f22SMatt Porter /* RTC base address */ 548b029f22SMatt Porter #define RTC_BASE 0x480C0000 558b029f22SMatt Porter 56c06e498aSLokesh Vutla /* OTG */ 57c06e498aSLokesh Vutla #define USB0_OTG_BASE 0x47401000 58c06e498aSLokesh Vutla #define USB1_OTG_BASE 0x47401800 59c06e498aSLokesh Vutla 60b43c17cbSMatt Porter #endif /* __AM33XX_HARDWARE_TI814X_H */ 61