1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25655108aSChandan Nath /* 35655108aSChandan Nath * hardware.h 45655108aSChandan Nath * 55655108aSChandan Nath * hardware specific header 65655108aSChandan Nath * 73ba65f97SMatt Porter * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 85655108aSChandan Nath */ 95655108aSChandan Nath 105655108aSChandan Nath #ifndef __AM33XX_HARDWARE_H 115655108aSChandan Nath #define __AM33XX_HARDWARE_H 125655108aSChandan Nath 138b029f22SMatt Porter #include <config.h> 1441aebf81STom Rini #include <asm/arch/omap.h> 153ba65f97SMatt Porter #ifdef CONFIG_AM33XX 163ba65f97SMatt Porter #include <asm/arch/hardware_am33xx.h> 17dcf846d5STENART Antoine #elif defined(CONFIG_TI816X) 18dcf846d5STENART Antoine #include <asm/arch/hardware_ti816x.h> 193ba65f97SMatt Porter #elif defined(CONFIG_TI814X) 203ba65f97SMatt Porter #include <asm/arch/hardware_ti814x.h> 21c06e498aSLokesh Vutla #elif defined(CONFIG_AM43XX) 22c06e498aSLokesh Vutla #include <asm/arch/hardware_am43xx.h> 233ba65f97SMatt Porter #endif 2441aebf81STom Rini 258b029f22SMatt Porter /* 268b029f22SMatt Porter * Common hardware definitions 278b029f22SMatt Porter */ 285655108aSChandan Nath 295655108aSChandan Nath /* DM Timer base addresses */ 305655108aSChandan Nath #define DM_TIMER0_BASE 0x4802C000 315655108aSChandan Nath #define DM_TIMER1_BASE 0x4802E000 325655108aSChandan Nath #define DM_TIMER2_BASE 0x48040000 335655108aSChandan Nath #define DM_TIMER3_BASE 0x48042000 345655108aSChandan Nath #define DM_TIMER4_BASE 0x48044000 355655108aSChandan Nath #define DM_TIMER5_BASE 0x48046000 365655108aSChandan Nath #define DM_TIMER6_BASE 0x48048000 375655108aSChandan Nath #define DM_TIMER7_BASE 0x4804A000 385655108aSChandan Nath 395655108aSChandan Nath /* GPIO Base address */ 405655108aSChandan Nath #define GPIO0_BASE 0x48032000 415655108aSChandan Nath #define GPIO1_BASE 0x4804C000 425655108aSChandan Nath 435655108aSChandan Nath /* BCH Error Location Module */ 445655108aSChandan Nath #define ELM_BASE 0x48080000 455655108aSChandan Nath 465655108aSChandan Nath /* EMIF Base address */ 475655108aSChandan Nath #define EMIF4_0_CFG_BASE 0x4C000000 485655108aSChandan Nath #define EMIF4_1_CFG_BASE 0x4D000000 495655108aSChandan Nath 505655108aSChandan Nath /* DDR Base address */ 515655108aSChandan Nath #define DDR_CTRL_ADDR 0x44E10E04 525655108aSChandan Nath #define DDR_CONTROL_BASE_ADDR 0x44E11404 535655108aSChandan Nath 545655108aSChandan Nath /* UART */ 5548c7f771SLandheer-Cieslak, Ronald #if CONFIG_CONS_INDEX == 1 565655108aSChandan Nath # define DEFAULT_UART_BASE UART0_BASE 5748c7f771SLandheer-Cieslak, Ronald #elif CONFIG_CONS_INDEX == 2 5848c7f771SLandheer-Cieslak, Ronald # define DEFAULT_UART_BASE UART1_BASE 5948c7f771SLandheer-Cieslak, Ronald #elif CONFIG_CONS_INDEX == 3 6048c7f771SLandheer-Cieslak, Ronald # define DEFAULT_UART_BASE UART2_BASE 6148c7f771SLandheer-Cieslak, Ronald #elif CONFIG_CONS_INDEX == 4 6248c7f771SLandheer-Cieslak, Ronald # define DEFAULT_UART_BASE UART3_BASE 6348c7f771SLandheer-Cieslak, Ronald #elif CONFIG_CONS_INDEX == 5 6448c7f771SLandheer-Cieslak, Ronald # define DEFAULT_UART_BASE UART4_BASE 6548c7f771SLandheer-Cieslak, Ronald #elif CONFIG_CONS_INDEX == 6 6648c7f771SLandheer-Cieslak, Ronald # define DEFAULT_UART_BASE UART5_BASE 6748c7f771SLandheer-Cieslak, Ronald #endif 685655108aSChandan Nath 698eb16b7fSIlya Yanok /* GPMC Base address */ 708eb16b7fSIlya Yanok #define GPMC_BASE 0x50000000 718eb16b7fSIlya Yanok 72e79cd8ebSChandan Nath /* CPSW Config space */ 7381df2babSMatt Porter #define CPSW_BASE 0x4A100000 74000820b5SVaibhav Hiremath 75fbd6295dSLokesh Vutla /* Control status register */ 76fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) 77fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 78fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) 79fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 80fbd6295dSLokesh Vutla #define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) 81fbd6295dSLokesh Vutla #define CTRL_SYSBOOT_15_14_SHIFT 22 82fbd6295dSLokesh Vutla 83fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 84fbd6295dSLokesh Vutla #define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 85fbd6295dSLokesh Vutla 86fbd6295dSLokesh Vutla #define NUM_CRYSTAL_FREQ 0x4 87fbd6295dSLokesh Vutla 88b424aae4SHeiko Schocher int clk_get(int clk); 895655108aSChandan Nath #endif /* __AM33XX_HARDWARE_H */ 90