1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define BIT(x) (1 << x) 21 #define CL_BIT(x) (0 << x) 22 23 /* Timer register bits */ 24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 25 #define TCLR_AR BIT(1) /* Auto reload */ 26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 29 30 /* device type */ 31 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 32 #define TST_DEVICE 0x0 33 #define EMU_DEVICE 0x1 34 #define HS_DEVICE 0x2 35 #define GP_DEVICE 0x3 36 37 /* cpu-id for AM33XX and TI81XX family */ 38 #define AM335X 0xB944 39 #define TI81XX 0xB81E 40 #define DEVICE_ID (CTRL_BASE + 0x0600) 41 42 /* This gives the status of the boot mode pins on the evm */ 43 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 44 | BIT(3) | BIT(4)) 45 46 /* Reset control */ 47 #ifdef CONFIG_AM33XX 48 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) 49 #elif defined(CONFIG_TI814X) 50 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 51 #endif 52 #define PRM_RSTST (PRM_RSTCTRL + 8) 53 #define PRM_RSTCTRL_RESET 0x01 54 #define PRM_RSTST_WARM_RESET_MASK 0x232 55 56 #ifndef __KERNEL_STRICT_NAMES 57 #ifndef __ASSEMBLY__ 58 struct gpmc_cs { 59 u32 config1; /* 0x00 */ 60 u32 config2; /* 0x04 */ 61 u32 config3; /* 0x08 */ 62 u32 config4; /* 0x0C */ 63 u32 config5; /* 0x10 */ 64 u32 config6; /* 0x14 */ 65 u32 config7; /* 0x18 */ 66 u32 nand_cmd; /* 0x1C */ 67 u32 nand_adr; /* 0x20 */ 68 u32 nand_dat; /* 0x24 */ 69 u8 res[8]; /* blow up to 0x30 byte */ 70 }; 71 72 struct bch_res_0_3 { 73 u32 bch_result_x[4]; 74 }; 75 76 struct gpmc { 77 u8 res1[0x10]; 78 u32 sysconfig; /* 0x10 */ 79 u8 res2[0x4]; 80 u32 irqstatus; /* 0x18 */ 81 u32 irqenable; /* 0x1C */ 82 u8 res3[0x20]; 83 u32 timeout_control; /* 0x40 */ 84 u8 res4[0xC]; 85 u32 config; /* 0x50 */ 86 u32 status; /* 0x54 */ 87 u8 res5[0x8]; /* 0x58 */ 88 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 89 u8 res6[0x14]; /* 0x1E0 */ 90 u32 ecc_config; /* 0x1F4 */ 91 u32 ecc_control; /* 0x1F8 */ 92 u32 ecc_size_config; /* 0x1FC */ 93 u32 ecc1_result; /* 0x200 */ 94 u32 ecc2_result; /* 0x204 */ 95 u32 ecc3_result; /* 0x208 */ 96 u32 ecc4_result; /* 0x20C */ 97 u32 ecc5_result; /* 0x210 */ 98 u32 ecc6_result; /* 0x214 */ 99 u32 ecc7_result; /* 0x218 */ 100 u32 ecc8_result; /* 0x21C */ 101 u32 ecc9_result; /* 0x220 */ 102 u8 res7[12]; /* 0x224 */ 103 u32 testmomde_ctrl; /* 0x230 */ 104 u8 res8[12]; /* 0x234 */ 105 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 106 }; 107 108 /* Used for board specific gpmc initialization */ 109 extern struct gpmc *gpmc_cfg; 110 111 /* Encapsulating core pll registers */ 112 struct cm_wkuppll { 113 unsigned int wkclkstctrl; /* offset 0x00 */ 114 unsigned int wkctrlclkctrl; /* offset 0x04 */ 115 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 116 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 117 unsigned int resv2[4]; 118 unsigned int idlestdpllmpu; /* offset 0x20 */ 119 unsigned int resv3[2]; 120 unsigned int clkseldpllmpu; /* offset 0x2c */ 121 unsigned int resv4[1]; 122 unsigned int idlestdpllddr; /* offset 0x34 */ 123 unsigned int resv5[2]; 124 unsigned int clkseldpllddr; /* offset 0x40 */ 125 unsigned int resv6[4]; 126 unsigned int clkseldplldisp; /* offset 0x54 */ 127 unsigned int resv7[1]; 128 unsigned int idlestdpllcore; /* offset 0x5c */ 129 unsigned int resv8[2]; 130 unsigned int clkseldpllcore; /* offset 0x68 */ 131 unsigned int resv9[1]; 132 unsigned int idlestdpllper; /* offset 0x70 */ 133 unsigned int resv10[2]; 134 unsigned int clkdcoldodpllper; /* offset 0x7c */ 135 unsigned int divm4dpllcore; /* offset 0x80 */ 136 unsigned int divm5dpllcore; /* offset 0x84 */ 137 unsigned int clkmoddpllmpu; /* offset 0x88 */ 138 unsigned int clkmoddpllper; /* offset 0x8c */ 139 unsigned int clkmoddpllcore; /* offset 0x90 */ 140 unsigned int clkmoddpllddr; /* offset 0x94 */ 141 unsigned int clkmoddplldisp; /* offset 0x98 */ 142 unsigned int clkseldpllper; /* offset 0x9c */ 143 unsigned int divm2dpllddr; /* offset 0xA0 */ 144 unsigned int divm2dplldisp; /* offset 0xA4 */ 145 unsigned int divm2dpllmpu; /* offset 0xA8 */ 146 unsigned int divm2dpllper; /* offset 0xAC */ 147 unsigned int resv11[1]; 148 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 149 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 150 unsigned int resv12[7]; 151 unsigned int divm6dpllcore; /* offset 0xD8 */ 152 }; 153 154 /** 155 * Encapsulating peripheral functional clocks 156 * pll registers 157 */ 158 struct cm_perpll { 159 unsigned int l4lsclkstctrl; /* offset 0x00 */ 160 unsigned int l3sclkstctrl; /* offset 0x04 */ 161 unsigned int l4fwclkstctrl; /* offset 0x08 */ 162 unsigned int l3clkstctrl; /* offset 0x0c */ 163 unsigned int resv1; 164 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 165 unsigned int lcdclkctrl; /* offset 0x18 */ 166 unsigned int usb0clkctrl; /* offset 0x1C */ 167 unsigned int resv2; 168 unsigned int tptc0clkctrl; /* offset 0x24 */ 169 unsigned int emifclkctrl; /* offset 0x28 */ 170 unsigned int ocmcramclkctrl; /* offset 0x2c */ 171 unsigned int gpmcclkctrl; /* offset 0x30 */ 172 unsigned int mcasp0clkctrl; /* offset 0x34 */ 173 unsigned int uart5clkctrl; /* offset 0x38 */ 174 unsigned int mmc0clkctrl; /* offset 0x3C */ 175 unsigned int elmclkctrl; /* offset 0x40 */ 176 unsigned int i2c2clkctrl; /* offset 0x44 */ 177 unsigned int i2c1clkctrl; /* offset 0x48 */ 178 unsigned int spi0clkctrl; /* offset 0x4C */ 179 unsigned int spi1clkctrl; /* offset 0x50 */ 180 unsigned int resv3[3]; 181 unsigned int l4lsclkctrl; /* offset 0x60 */ 182 unsigned int l4fwclkctrl; /* offset 0x64 */ 183 unsigned int mcasp1clkctrl; /* offset 0x68 */ 184 unsigned int uart1clkctrl; /* offset 0x6C */ 185 unsigned int uart2clkctrl; /* offset 0x70 */ 186 unsigned int uart3clkctrl; /* offset 0x74 */ 187 unsigned int uart4clkctrl; /* offset 0x78 */ 188 unsigned int timer7clkctrl; /* offset 0x7C */ 189 unsigned int timer2clkctrl; /* offset 0x80 */ 190 unsigned int timer3clkctrl; /* offset 0x84 */ 191 unsigned int timer4clkctrl; /* offset 0x88 */ 192 unsigned int resv4[8]; 193 unsigned int gpio1clkctrl; /* offset 0xAC */ 194 unsigned int gpio2clkctrl; /* offset 0xB0 */ 195 unsigned int gpio3clkctrl; /* offset 0xB4 */ 196 unsigned int resv5; 197 unsigned int tpccclkctrl; /* offset 0xBC */ 198 unsigned int dcan0clkctrl; /* offset 0xC0 */ 199 unsigned int dcan1clkctrl; /* offset 0xC4 */ 200 unsigned int resv6[2]; 201 unsigned int emiffwclkctrl; /* offset 0xD0 */ 202 unsigned int resv7[2]; 203 unsigned int l3instrclkctrl; /* offset 0xDC */ 204 unsigned int l3clkctrl; /* Offset 0xE0 */ 205 unsigned int resv8[4]; 206 unsigned int mmc1clkctrl; /* offset 0xF4 */ 207 unsigned int mmc2clkctrl; /* offset 0xF8 */ 208 unsigned int resv9[8]; 209 unsigned int l4hsclkstctrl; /* offset 0x11C */ 210 unsigned int l4hsclkctrl; /* offset 0x120 */ 211 unsigned int resv10[8]; 212 unsigned int cpswclkstctrl; /* offset 0x144 */ 213 }; 214 215 /* Encapsulating Display pll registers */ 216 struct cm_dpll { 217 unsigned int resv1[2]; 218 unsigned int clktimer2clk; /* offset 0x08 */ 219 }; 220 221 /* Control Module RTC registers */ 222 struct cm_rtc { 223 unsigned int rtcclkctrl; /* offset 0x0 */ 224 unsigned int clkstctrl; /* offset 0x4 */ 225 }; 226 227 /* Watchdog timer registers */ 228 struct wd_timer { 229 unsigned int resv1[4]; 230 unsigned int wdtwdsc; /* offset 0x010 */ 231 unsigned int wdtwdst; /* offset 0x014 */ 232 unsigned int wdtwisr; /* offset 0x018 */ 233 unsigned int wdtwier; /* offset 0x01C */ 234 unsigned int wdtwwer; /* offset 0x020 */ 235 unsigned int wdtwclr; /* offset 0x024 */ 236 unsigned int wdtwcrr; /* offset 0x028 */ 237 unsigned int wdtwldr; /* offset 0x02C */ 238 unsigned int wdtwtgr; /* offset 0x030 */ 239 unsigned int wdtwwps; /* offset 0x034 */ 240 unsigned int resv2[3]; 241 unsigned int wdtwdly; /* offset 0x044 */ 242 unsigned int wdtwspr; /* offset 0x048 */ 243 unsigned int resv3[1]; 244 unsigned int wdtwqeoi; /* offset 0x050 */ 245 unsigned int wdtwqstar; /* offset 0x054 */ 246 unsigned int wdtwqsta; /* offset 0x058 */ 247 unsigned int wdtwqens; /* offset 0x05C */ 248 unsigned int wdtwqenc; /* offset 0x060 */ 249 unsigned int resv4[39]; 250 unsigned int wdt_unfr; /* offset 0x100 */ 251 }; 252 253 /* Timer 32 bit registers */ 254 struct gptimer { 255 unsigned int tidr; /* offset 0x00 */ 256 unsigned char res1[12]; 257 unsigned int tiocp_cfg; /* offset 0x10 */ 258 unsigned char res2[12]; 259 unsigned int tier; /* offset 0x20 */ 260 unsigned int tistatr; /* offset 0x24 */ 261 unsigned int tistat; /* offset 0x28 */ 262 unsigned int tisr; /* offset 0x2c */ 263 unsigned int tcicr; /* offset 0x30 */ 264 unsigned int twer; /* offset 0x34 */ 265 unsigned int tclr; /* offset 0x38 */ 266 unsigned int tcrr; /* offset 0x3c */ 267 unsigned int tldr; /* offset 0x40 */ 268 unsigned int ttgr; /* offset 0x44 */ 269 unsigned int twpc; /* offset 0x48 */ 270 unsigned int tmar; /* offset 0x4c */ 271 unsigned int tcar1; /* offset 0x50 */ 272 unsigned int tscir; /* offset 0x54 */ 273 unsigned int tcar2; /* offset 0x58 */ 274 }; 275 276 /* RTC Registers */ 277 struct rtc_regs { 278 unsigned int res[21]; 279 unsigned int osc; /* offset 0x54 */ 280 unsigned int res2[5]; 281 unsigned int kick0r; /* offset 0x6c */ 282 unsigned int kick1r; /* offset 0x70 */ 283 }; 284 285 /* UART Registers */ 286 struct uart_sys { 287 unsigned int resv1[21]; 288 unsigned int uartsyscfg; /* offset 0x54 */ 289 unsigned int uartsyssts; /* offset 0x58 */ 290 }; 291 292 /* VTP Registers */ 293 struct vtp_reg { 294 unsigned int vtp0ctrlreg; 295 }; 296 297 /* Control Status Register */ 298 struct ctrl_stat { 299 unsigned int resv1[16]; 300 unsigned int statusreg; /* ofset 0x40 */ 301 unsigned int resv2[51]; 302 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 303 }; 304 305 /* AM33XX GPIO registers */ 306 #define OMAP_GPIO_REVISION 0x0000 307 #define OMAP_GPIO_SYSCONFIG 0x0010 308 #define OMAP_GPIO_SYSSTATUS 0x0114 309 #define OMAP_GPIO_IRQSTATUS1 0x002c 310 #define OMAP_GPIO_IRQSTATUS2 0x0030 311 #define OMAP_GPIO_CTRL 0x0130 312 #define OMAP_GPIO_OE 0x0134 313 #define OMAP_GPIO_DATAIN 0x0138 314 #define OMAP_GPIO_DATAOUT 0x013c 315 #define OMAP_GPIO_LEVELDETECT0 0x0140 316 #define OMAP_GPIO_LEVELDETECT1 0x0144 317 #define OMAP_GPIO_RISINGDETECT 0x0148 318 #define OMAP_GPIO_FALLINGDETECT 0x014c 319 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 320 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 321 #define OMAP_GPIO_CLEARDATAOUT 0x0190 322 #define OMAP_GPIO_SETDATAOUT 0x0194 323 324 /* Control Device Register */ 325 struct ctrl_dev { 326 unsigned int deviceid; /* offset 0x00 */ 327 unsigned int resv1[7]; 328 unsigned int usb_ctrl0; /* offset 0x20 */ 329 unsigned int resv2; 330 unsigned int usb_ctrl1; /* offset 0x28 */ 331 unsigned int resv3; 332 unsigned int macid0l; /* offset 0x30 */ 333 unsigned int macid0h; /* offset 0x34 */ 334 unsigned int macid1l; /* offset 0x38 */ 335 unsigned int macid1h; /* offset 0x3c */ 336 unsigned int resv4[4]; 337 unsigned int miisel; /* offset 0x50 */ 338 }; 339 #endif /* __ASSEMBLY__ */ 340 #endif /* __KERNEL_STRICT_NAMES */ 341 342 #endif /* _AM33XX_CPU_H */ 343