1*18a952ceSMichal Simek// SPDX-License-Identifier: GPL-2.0+ 21f4f3d33SMichal Simek/* 31f4f3d33SMichal Simek * dts file for Xilinx ZynqMP ZCU102 RevB 41f4f3d33SMichal Simek * 5*18a952ceSMichal Simek * (C) Copyright 2016 - 2018, Xilinx, Inc. 61f4f3d33SMichal Simek * 71f4f3d33SMichal Simek * Michal Simek <michal.simek@xilinx.com> 81f4f3d33SMichal Simek */ 91f4f3d33SMichal Simek 10be463451SMichal Simek#include "zynqmp-zcu102-revA.dts" 111f4f3d33SMichal Simek 121f4f3d33SMichal Simek/ { 131f4f3d33SMichal Simek model = "ZynqMP ZCU102 RevB"; 14582ee924SMichal Simek compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 151f4f3d33SMichal Simek}; 161f4f3d33SMichal Simek 171f4f3d33SMichal Simek&gem3 { 181f4f3d33SMichal Simek phy-handle = <&phyc>; 191f4f3d33SMichal Simek phyc: phy@c { 201f4f3d33SMichal Simek reg = <0xc>; 211f4f3d33SMichal Simek ti,rx-internal-delay = <0x8>; 221f4f3d33SMichal Simek ti,tx-internal-delay = <0xa>; 231f4f3d33SMichal Simek ti,fifo-depth = <0x1>; 241f4f3d33SMichal Simek }; 251f4f3d33SMichal Simek /* Cleanup from RevA */ 261f4f3d33SMichal Simek /delete-node/ phy@21; 271f4f3d33SMichal Simek}; 281f4f3d33SMichal Simek 291f4f3d33SMichal Simek/* Fix collision with u61 */ 301f4f3d33SMichal Simek&i2c0 { 31ba7b6dfaSMichal Simek i2c-mux@75 { 321f4f3d33SMichal Simek i2c@2 { 331f4f3d33SMichal Simek max15303@1b { /* u8 */ 34a16e5786SMichal Simek compatible = "maxim,max15303"; 351f4f3d33SMichal Simek reg = <0x1b>; 361f4f3d33SMichal Simek }; 371f4f3d33SMichal Simek /delete-node/ max15303@20; 381f4f3d33SMichal Simek }; 391f4f3d33SMichal Simek }; 401f4f3d33SMichal Simek}; 41