1*eebbfd86SSiva Durga Prasad Paladugu// SPDX-License-Identifier: GPL-2.0 2*eebbfd86SSiva Durga Prasad Paladugu/* 3*eebbfd86SSiva Durga Prasad Paladugu * dts file for Xilinx Versal Mini Configuration 4*eebbfd86SSiva Durga Prasad Paladugu * 5*eebbfd86SSiva Durga Prasad Paladugu * (C) Copyright 2019, Xilinx, Inc. 6*eebbfd86SSiva Durga Prasad Paladugu * 7*eebbfd86SSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 8*eebbfd86SSiva Durga Prasad Paladugu */ 9*eebbfd86SSiva Durga Prasad Paladugu 10*eebbfd86SSiva Durga Prasad Paladugu/dts-v1/; 11*eebbfd86SSiva Durga Prasad Paladugu 12*eebbfd86SSiva Durga Prasad Paladugu/ { 13*eebbfd86SSiva Durga Prasad Paladugu model = "Versal MINI"; 14*eebbfd86SSiva Durga Prasad Paladugu compatible = "xlnx,versal"; 15*eebbfd86SSiva Durga Prasad Paladugu #address-cells = <2>; 16*eebbfd86SSiva Durga Prasad Paladugu #size-cells = <2>; 17*eebbfd86SSiva Durga Prasad Paladugu 18*eebbfd86SSiva Durga Prasad Paladugu aliases { 19*eebbfd86SSiva Durga Prasad Paladugu serial0 = &dcc; 20*eebbfd86SSiva Durga Prasad Paladugu }; 21*eebbfd86SSiva Durga Prasad Paladugu 22*eebbfd86SSiva Durga Prasad Paladugu chosen { 23*eebbfd86SSiva Durga Prasad Paladugu stdout-path = "serial0:115200n8"; 24*eebbfd86SSiva Durga Prasad Paladugu }; 25*eebbfd86SSiva Durga Prasad Paladugu 26*eebbfd86SSiva Durga Prasad Paladugu memory@0 { 27*eebbfd86SSiva Durga Prasad Paladugu device_type = "memory"; 28*eebbfd86SSiva Durga Prasad Paladugu reg = <0x0 0xfffc0000 0x0 0x40000>, <0x0 0x0 0x0 0x80000000>; 29*eebbfd86SSiva Durga Prasad Paladugu }; 30*eebbfd86SSiva Durga Prasad Paladugu 31*eebbfd86SSiva Durga Prasad Paladugu dcc: dcc { 32*eebbfd86SSiva Durga Prasad Paladugu compatible = "arm,dcc"; 33*eebbfd86SSiva Durga Prasad Paladugu status = "okay"; 34*eebbfd86SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 35*eebbfd86SSiva Durga Prasad Paladugu }; 36*eebbfd86SSiva Durga Prasad Paladugu}; 37