15ab502cbSMasahiro Yamada/dts-v1/; 25ab502cbSMasahiro Yamada 3*ce02a71cSSimon Glass#include <dt-bindings/input/input.h> 45ab502cbSMasahiro Yamada#include "tegra20.dtsi" 55ab502cbSMasahiro Yamada 65ab502cbSMasahiro Yamada/ { 75ab502cbSMasahiro Yamada model = "NVIDIA Seaboard"; 85ab502cbSMasahiro Yamada compatible = "nvidia,seaboard", "nvidia,tegra20"; 95ab502cbSMasahiro Yamada 105ab502cbSMasahiro Yamada aliases { 115ab502cbSMasahiro Yamada /* This defines the order of our ports */ 125ab502cbSMasahiro Yamada usb0 = "/usb@c5008000"; 135ab502cbSMasahiro Yamada usb1 = "/usb@c5000000"; 145ab502cbSMasahiro Yamada i2c0 = "/i2c@7000d000"; 155ab502cbSMasahiro Yamada i2c1 = "/i2c@7000c000"; 165ab502cbSMasahiro Yamada i2c2 = "/i2c@7000c400"; 175ab502cbSMasahiro Yamada i2c3 = "/i2c@7000c500"; 18*ce02a71cSSimon Glass rtc0 = "/i2c@7000d000/tps6586x@34"; 19*ce02a71cSSimon Glass rtc1 = "/rtc@7000e000"; 20*ce02a71cSSimon Glass serial0 = &uartd; 215ab502cbSMasahiro Yamada sdhci0 = "/sdhci@c8000600"; 225ab502cbSMasahiro Yamada sdhci1 = "/sdhci@c8000400"; 235ab502cbSMasahiro Yamada }; 245ab502cbSMasahiro Yamada 25*ce02a71cSSimon Glass chosen { 26*ce02a71cSSimon Glass bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; 27*ce02a71cSSimon Glass }; 28*ce02a71cSSimon Glass 29*ce02a71cSSimon Glass chosen { 30*ce02a71cSSimon Glass stdout-path = &uartd; 31*ce02a71cSSimon Glass }; 32*ce02a71cSSimon Glass 335ab502cbSMasahiro Yamada memory { 345ab502cbSMasahiro Yamada reg = <0x00000000 0x40000000>; 355ab502cbSMasahiro Yamada }; 365ab502cbSMasahiro Yamada 37ee7d755aSSimon Glass host1x@50000000 { 385ab502cbSMasahiro Yamada status = "okay"; 395ab502cbSMasahiro Yamada dc@54200000 { 405ab502cbSMasahiro Yamada status = "okay"; 415ab502cbSMasahiro Yamada rgb { 425ab502cbSMasahiro Yamada status = "okay"; 43*ce02a71cSSimon Glass 44*ce02a71cSSimon Glass nvidia,panel = <&panel>; 455ab502cbSMasahiro Yamada }; 465ab502cbSMasahiro Yamada }; 475ab502cbSMasahiro Yamada 48*ce02a71cSSimon Glass hdmi@54280000 { 49ee7d755aSSimon Glass status = "okay"; 505ab502cbSMasahiro Yamada 51*ce02a71cSSimon Glass vdd-supply = <&hdmi_vdd_reg>; 52*ce02a71cSSimon Glass pll-supply = <&hdmi_pll_reg>; 53*ce02a71cSSimon Glass hdmi-supply = <&vdd_hdmi>; 54*ce02a71cSSimon Glass 55*ce02a71cSSimon Glass nvidia,ddc-i2c-bus = <&hdmi_ddc>; 56*ce02a71cSSimon Glass nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 57*ce02a71cSSimon Glass GPIO_ACTIVE_HIGH>; 585ab502cbSMasahiro Yamada }; 595ab502cbSMasahiro Yamada }; 60*ce02a71cSSimon Glass 61*ce02a71cSSimon Glass pinmux@70000014 { 62*ce02a71cSSimon Glass pinctrl-names = "default"; 63*ce02a71cSSimon Glass pinctrl-0 = <&state_default>; 64*ce02a71cSSimon Glass 65*ce02a71cSSimon Glass state_default: pinmux { 66*ce02a71cSSimon Glass ata { 67*ce02a71cSSimon Glass nvidia,pins = "ata"; 68*ce02a71cSSimon Glass nvidia,function = "ide"; 69*ce02a71cSSimon Glass }; 70*ce02a71cSSimon Glass atb { 71*ce02a71cSSimon Glass nvidia,pins = "atb", "gma", "gme"; 72*ce02a71cSSimon Glass nvidia,function = "sdio4"; 73*ce02a71cSSimon Glass }; 74*ce02a71cSSimon Glass atc { 75*ce02a71cSSimon Glass nvidia,pins = "atc"; 76*ce02a71cSSimon Glass nvidia,function = "nand"; 77*ce02a71cSSimon Glass }; 78*ce02a71cSSimon Glass atd { 79*ce02a71cSSimon Glass nvidia,pins = "atd", "ate", "gmb", "spia", 80*ce02a71cSSimon Glass "spib", "spic"; 81*ce02a71cSSimon Glass nvidia,function = "gmi"; 82*ce02a71cSSimon Glass }; 83*ce02a71cSSimon Glass cdev1 { 84*ce02a71cSSimon Glass nvidia,pins = "cdev1"; 85*ce02a71cSSimon Glass nvidia,function = "plla_out"; 86*ce02a71cSSimon Glass }; 87*ce02a71cSSimon Glass cdev2 { 88*ce02a71cSSimon Glass nvidia,pins = "cdev2"; 89*ce02a71cSSimon Glass nvidia,function = "pllp_out4"; 90*ce02a71cSSimon Glass }; 91*ce02a71cSSimon Glass crtp { 92*ce02a71cSSimon Glass nvidia,pins = "crtp", "lm1"; 93*ce02a71cSSimon Glass nvidia,function = "crt"; 94*ce02a71cSSimon Glass }; 95*ce02a71cSSimon Glass csus { 96*ce02a71cSSimon Glass nvidia,pins = "csus"; 97*ce02a71cSSimon Glass nvidia,function = "vi_sensor_clk"; 98*ce02a71cSSimon Glass }; 99*ce02a71cSSimon Glass dap1 { 100*ce02a71cSSimon Glass nvidia,pins = "dap1"; 101*ce02a71cSSimon Glass nvidia,function = "dap1"; 102*ce02a71cSSimon Glass }; 103*ce02a71cSSimon Glass dap2 { 104*ce02a71cSSimon Glass nvidia,pins = "dap2"; 105*ce02a71cSSimon Glass nvidia,function = "dap2"; 106*ce02a71cSSimon Glass }; 107*ce02a71cSSimon Glass dap3 { 108*ce02a71cSSimon Glass nvidia,pins = "dap3"; 109*ce02a71cSSimon Glass nvidia,function = "dap3"; 110*ce02a71cSSimon Glass }; 111*ce02a71cSSimon Glass dap4 { 112*ce02a71cSSimon Glass nvidia,pins = "dap4"; 113*ce02a71cSSimon Glass nvidia,function = "dap4"; 114*ce02a71cSSimon Glass }; 115*ce02a71cSSimon Glass dta { 116*ce02a71cSSimon Glass nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 117*ce02a71cSSimon Glass nvidia,function = "vi"; 118*ce02a71cSSimon Glass }; 119*ce02a71cSSimon Glass dtf { 120*ce02a71cSSimon Glass nvidia,pins = "dtf"; 121*ce02a71cSSimon Glass nvidia,function = "i2c3"; 122*ce02a71cSSimon Glass }; 123*ce02a71cSSimon Glass gmc { 124*ce02a71cSSimon Glass nvidia,pins = "gmc"; 125*ce02a71cSSimon Glass nvidia,function = "uartd"; 126*ce02a71cSSimon Glass }; 127*ce02a71cSSimon Glass gmd { 128*ce02a71cSSimon Glass nvidia,pins = "gmd"; 129*ce02a71cSSimon Glass nvidia,function = "sflash"; 130*ce02a71cSSimon Glass }; 131*ce02a71cSSimon Glass gpu { 132*ce02a71cSSimon Glass nvidia,pins = "gpu"; 133*ce02a71cSSimon Glass nvidia,function = "pwm"; 134*ce02a71cSSimon Glass }; 135*ce02a71cSSimon Glass gpu7 { 136*ce02a71cSSimon Glass nvidia,pins = "gpu7"; 137*ce02a71cSSimon Glass nvidia,function = "rtck"; 138*ce02a71cSSimon Glass }; 139*ce02a71cSSimon Glass gpv { 140*ce02a71cSSimon Glass nvidia,pins = "gpv", "slxa", "slxk"; 141*ce02a71cSSimon Glass nvidia,function = "pcie"; 142*ce02a71cSSimon Glass }; 143*ce02a71cSSimon Glass hdint { 144*ce02a71cSSimon Glass nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", 145*ce02a71cSSimon Glass "lsck", "lsda"; 146*ce02a71cSSimon Glass nvidia,function = "hdmi"; 147*ce02a71cSSimon Glass }; 148*ce02a71cSSimon Glass i2cp { 149*ce02a71cSSimon Glass nvidia,pins = "i2cp"; 150*ce02a71cSSimon Glass nvidia,function = "i2cp"; 151*ce02a71cSSimon Glass }; 152*ce02a71cSSimon Glass irrx { 153*ce02a71cSSimon Glass nvidia,pins = "irrx", "irtx"; 154*ce02a71cSSimon Glass nvidia,function = "uartb"; 155*ce02a71cSSimon Glass }; 156*ce02a71cSSimon Glass kbca { 157*ce02a71cSSimon Glass nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 158*ce02a71cSSimon Glass "kbce", "kbcf"; 159*ce02a71cSSimon Glass nvidia,function = "kbc"; 160*ce02a71cSSimon Glass }; 161*ce02a71cSSimon Glass lcsn { 162*ce02a71cSSimon Glass nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", 163*ce02a71cSSimon Glass "lsdi", "lvp0"; 164*ce02a71cSSimon Glass nvidia,function = "rsvd4"; 165*ce02a71cSSimon Glass }; 166*ce02a71cSSimon Glass ld0 { 167*ce02a71cSSimon Glass nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 168*ce02a71cSSimon Glass "ld5", "ld6", "ld7", "ld8", "ld9", 169*ce02a71cSSimon Glass "ld10", "ld11", "ld12", "ld13", "ld14", 170*ce02a71cSSimon Glass "ld15", "ld16", "ld17", "ldi", "lhp0", 171*ce02a71cSSimon Glass "lhp1", "lhp2", "lhs", "lpp", "lsc0", 172*ce02a71cSSimon Glass "lspi", "lvp1", "lvs"; 173*ce02a71cSSimon Glass nvidia,function = "displaya"; 174*ce02a71cSSimon Glass }; 175*ce02a71cSSimon Glass owc { 176*ce02a71cSSimon Glass nvidia,pins = "owc", "spdi", "spdo", "uac"; 177*ce02a71cSSimon Glass nvidia,function = "rsvd2"; 178*ce02a71cSSimon Glass }; 179*ce02a71cSSimon Glass pmc { 180*ce02a71cSSimon Glass nvidia,pins = "pmc"; 181*ce02a71cSSimon Glass nvidia,function = "pwr_on"; 182*ce02a71cSSimon Glass }; 183*ce02a71cSSimon Glass rm { 184*ce02a71cSSimon Glass nvidia,pins = "rm"; 185*ce02a71cSSimon Glass nvidia,function = "i2c1"; 186*ce02a71cSSimon Glass }; 187*ce02a71cSSimon Glass sdb { 188*ce02a71cSSimon Glass nvidia,pins = "sdb", "sdc", "sdd"; 189*ce02a71cSSimon Glass nvidia,function = "sdio3"; 190*ce02a71cSSimon Glass }; 191*ce02a71cSSimon Glass sdio1 { 192*ce02a71cSSimon Glass nvidia,pins = "sdio1"; 193*ce02a71cSSimon Glass nvidia,function = "sdio1"; 194*ce02a71cSSimon Glass }; 195*ce02a71cSSimon Glass slxc { 196*ce02a71cSSimon Glass nvidia,pins = "slxc", "slxd"; 197*ce02a71cSSimon Glass nvidia,function = "spdif"; 198*ce02a71cSSimon Glass }; 199*ce02a71cSSimon Glass spid { 200*ce02a71cSSimon Glass nvidia,pins = "spid", "spie", "spif"; 201*ce02a71cSSimon Glass nvidia,function = "spi1"; 202*ce02a71cSSimon Glass }; 203*ce02a71cSSimon Glass spig { 204*ce02a71cSSimon Glass nvidia,pins = "spig", "spih"; 205*ce02a71cSSimon Glass nvidia,function = "spi2_alt"; 206*ce02a71cSSimon Glass }; 207*ce02a71cSSimon Glass uaa { 208*ce02a71cSSimon Glass nvidia,pins = "uaa", "uab", "uda"; 209*ce02a71cSSimon Glass nvidia,function = "ulpi"; 210*ce02a71cSSimon Glass }; 211*ce02a71cSSimon Glass uad { 212*ce02a71cSSimon Glass nvidia,pins = "uad"; 213*ce02a71cSSimon Glass nvidia,function = "irda"; 214*ce02a71cSSimon Glass }; 215*ce02a71cSSimon Glass uca { 216*ce02a71cSSimon Glass nvidia,pins = "uca", "ucb"; 217*ce02a71cSSimon Glass nvidia,function = "uartc"; 218*ce02a71cSSimon Glass }; 219*ce02a71cSSimon Glass conf_ata { 220*ce02a71cSSimon Glass nvidia,pins = "ata", "atb", "atc", "atd", 221*ce02a71cSSimon Glass "cdev1", "cdev2", "dap1", "dap2", 222*ce02a71cSSimon Glass "dap4", "ddc", "dtf", "gma", "gmc", "gmd", 223*ce02a71cSSimon Glass "gme", "gpu", "gpu7", "i2cp", "irrx", 224*ce02a71cSSimon Glass "irtx", "pta", "rm", "sdc", "sdd", 225*ce02a71cSSimon Glass "slxd", "slxk", "spdi", "spdo", "uac", 226*ce02a71cSSimon Glass "uad", "uca", "ucb", "uda"; 227*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_NONE>; 228*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_DISABLE>; 229*ce02a71cSSimon Glass }; 230*ce02a71cSSimon Glass conf_ate { 231*ce02a71cSSimon Glass nvidia,pins = "ate", "csus", "dap3", 232*ce02a71cSSimon Glass "gpv", "owc", "slxc", "spib", "spid", 233*ce02a71cSSimon Glass "spie"; 234*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_NONE>; 235*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_ENABLE>; 236*ce02a71cSSimon Glass }; 237*ce02a71cSSimon Glass conf_ck32 { 238*ce02a71cSSimon Glass nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 239*ce02a71cSSimon Glass "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 240*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_NONE>; 241*ce02a71cSSimon Glass }; 242*ce02a71cSSimon Glass conf_crtp { 243*ce02a71cSSimon Glass nvidia,pins = "crtp", "gmb", "slxa", "spia", 244*ce02a71cSSimon Glass "spig", "spih"; 245*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_UP>; 246*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_ENABLE>; 247*ce02a71cSSimon Glass }; 248*ce02a71cSSimon Glass conf_dta { 249*ce02a71cSSimon Glass nvidia,pins = "dta", "dtb", "dtc", "dtd"; 250*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 251*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_DISABLE>; 252*ce02a71cSSimon Glass }; 253*ce02a71cSSimon Glass conf_dte { 254*ce02a71cSSimon Glass nvidia,pins = "dte", "spif"; 255*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 256*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_ENABLE>; 257*ce02a71cSSimon Glass }; 258*ce02a71cSSimon Glass conf_hdint { 259*ce02a71cSSimon Glass nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 260*ce02a71cSSimon Glass "lpw1", "lsc1", "lsck", "lsda", "lsdi", 261*ce02a71cSSimon Glass "lvp0"; 262*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_ENABLE>; 263*ce02a71cSSimon Glass }; 264*ce02a71cSSimon Glass conf_kbca { 265*ce02a71cSSimon Glass nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 266*ce02a71cSSimon Glass "kbce", "kbcf", "sdio1", "spic", "uaa", 267*ce02a71cSSimon Glass "uab"; 268*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_UP>; 269*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*ce02a71cSSimon Glass }; 271*ce02a71cSSimon Glass conf_lc { 272*ce02a71cSSimon Glass nvidia,pins = "lc", "ls"; 273*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_UP>; 274*ce02a71cSSimon Glass }; 275*ce02a71cSSimon Glass conf_ld0 { 276*ce02a71cSSimon Glass nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 277*ce02a71cSSimon Glass "ld5", "ld6", "ld7", "ld8", "ld9", 278*ce02a71cSSimon Glass "ld10", "ld11", "ld12", "ld13", "ld14", 279*ce02a71cSSimon Glass "ld15", "ld16", "ld17", "ldi", "lhp0", 280*ce02a71cSSimon Glass "lhp1", "lhp2", "lhs", "lm0", "lpp", 281*ce02a71cSSimon Glass "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 282*ce02a71cSSimon Glass "lvs", "pmc", "sdb"; 283*ce02a71cSSimon Glass nvidia,tristate = <TEGRA_PIN_DISABLE>; 284*ce02a71cSSimon Glass }; 285*ce02a71cSSimon Glass conf_ld17_0 { 286*ce02a71cSSimon Glass nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 287*ce02a71cSSimon Glass "ld23_22"; 288*ce02a71cSSimon Glass nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 289*ce02a71cSSimon Glass }; 290*ce02a71cSSimon Glass drive_sdio1 { 291*ce02a71cSSimon Glass nvidia,pins = "drive_sdio1"; 292*ce02a71cSSimon Glass nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 293*ce02a71cSSimon Glass nvidia,schmitt = <TEGRA_PIN_DISABLE>; 294*ce02a71cSSimon Glass nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 295*ce02a71cSSimon Glass nvidia,pull-down-strength = <31>; 296*ce02a71cSSimon Glass nvidia,pull-up-strength = <31>; 297*ce02a71cSSimon Glass nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 298*ce02a71cSSimon Glass nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 299*ce02a71cSSimon Glass }; 300*ce02a71cSSimon Glass }; 301*ce02a71cSSimon Glass 302*ce02a71cSSimon Glass state_i2cmux_ddc: pinmux_i2cmux_ddc { 303*ce02a71cSSimon Glass ddc { 304*ce02a71cSSimon Glass nvidia,pins = "ddc"; 305*ce02a71cSSimon Glass nvidia,function = "i2c2"; 306*ce02a71cSSimon Glass }; 307*ce02a71cSSimon Glass pta { 308*ce02a71cSSimon Glass nvidia,pins = "pta"; 309*ce02a71cSSimon Glass nvidia,function = "rsvd4"; 310*ce02a71cSSimon Glass }; 311*ce02a71cSSimon Glass }; 312*ce02a71cSSimon Glass 313*ce02a71cSSimon Glass state_i2cmux_pta: pinmux_i2cmux_pta { 314*ce02a71cSSimon Glass ddc { 315*ce02a71cSSimon Glass nvidia,pins = "ddc"; 316*ce02a71cSSimon Glass nvidia,function = "rsvd4"; 317*ce02a71cSSimon Glass }; 318*ce02a71cSSimon Glass pta { 319*ce02a71cSSimon Glass nvidia,pins = "pta"; 320*ce02a71cSSimon Glass nvidia,function = "i2c2"; 321*ce02a71cSSimon Glass }; 322*ce02a71cSSimon Glass }; 323*ce02a71cSSimon Glass 324*ce02a71cSSimon Glass state_i2cmux_idle: pinmux_i2cmux_idle { 325*ce02a71cSSimon Glass ddc { 326*ce02a71cSSimon Glass nvidia,pins = "ddc"; 327*ce02a71cSSimon Glass nvidia,function = "rsvd4"; 328*ce02a71cSSimon Glass }; 329*ce02a71cSSimon Glass pta { 330*ce02a71cSSimon Glass nvidia,pins = "pta"; 331*ce02a71cSSimon Glass nvidia,function = "rsvd4"; 332*ce02a71cSSimon Glass }; 333*ce02a71cSSimon Glass }; 334*ce02a71cSSimon Glass }; 335*ce02a71cSSimon Glass 336*ce02a71cSSimon Glass i2s@70002800 { 337*ce02a71cSSimon Glass status = "okay"; 3385ab502cbSMasahiro Yamada }; 3395ab502cbSMasahiro Yamada 3405ab502cbSMasahiro Yamada serial@70006300 { 341*ce02a71cSSimon Glass status = "okay"; 3425ab502cbSMasahiro Yamada clock-frequency = < 216000000 >; 3435ab502cbSMasahiro Yamada }; 3445ab502cbSMasahiro Yamada 3455ab502cbSMasahiro Yamada nand-controller@70008000 { 3462b2b50bcSSimon Glass nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 3475ab502cbSMasahiro Yamada nvidia,width = <8>; 3485ab502cbSMasahiro Yamada nvidia,timing = <26 100 20 80 20 10 12 10 70>; 3495ab502cbSMasahiro Yamada nand@0 { 3505ab502cbSMasahiro Yamada reg = <0>; 3515ab502cbSMasahiro Yamada compatible = "hynix,hy27uf4g2b", "nand-flash"; 3525ab502cbSMasahiro Yamada }; 3535ab502cbSMasahiro Yamada }; 3545ab502cbSMasahiro Yamada 355*ce02a71cSSimon Glass pwm: pwm@7000a000 { 356*ce02a71cSSimon Glass status = "okay"; 357*ce02a71cSSimon Glass }; 358*ce02a71cSSimon Glass 3595ab502cbSMasahiro Yamada i2c@7000c000 { 360ee7d755aSSimon Glass status = "okay"; 361*ce02a71cSSimon Glass clock-frequency = <400000>; 362*ce02a71cSSimon Glass 363*ce02a71cSSimon Glass wm8903: wm8903@1a { 364*ce02a71cSSimon Glass compatible = "wlf,wm8903"; 365*ce02a71cSSimon Glass reg = <0x1a>; 366*ce02a71cSSimon Glass interrupt-parent = <&gpio>; 367*ce02a71cSSimon Glass interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 368*ce02a71cSSimon Glass 369*ce02a71cSSimon Glass gpio-controller; 370*ce02a71cSSimon Glass #gpio-cells = <2>; 371*ce02a71cSSimon Glass 372*ce02a71cSSimon Glass micdet-cfg = <0>; 373*ce02a71cSSimon Glass micdet-delay = <100>; 374*ce02a71cSSimon Glass gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 375*ce02a71cSSimon Glass }; 376*ce02a71cSSimon Glass 377*ce02a71cSSimon Glass /* ALS and proximity sensor */ 378*ce02a71cSSimon Glass isl29018@44 { 379*ce02a71cSSimon Glass compatible = "isil,isl29018"; 380*ce02a71cSSimon Glass reg = <0x44>; 381*ce02a71cSSimon Glass interrupt-parent = <&gpio>; 382*ce02a71cSSimon Glass interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 383*ce02a71cSSimon Glass }; 384*ce02a71cSSimon Glass 385*ce02a71cSSimon Glass gyrometer@68 { 386*ce02a71cSSimon Glass compatible = "invn,mpu3050"; 387*ce02a71cSSimon Glass reg = <0x68>; 388*ce02a71cSSimon Glass interrupt-parent = <&gpio>; 389*ce02a71cSSimon Glass interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; 390*ce02a71cSSimon Glass }; 3915ab502cbSMasahiro Yamada }; 3925ab502cbSMasahiro Yamada 3935ab502cbSMasahiro Yamada i2c@7000c400 { 394ee7d755aSSimon Glass status = "okay"; 395*ce02a71cSSimon Glass clock-frequency = <100000>; 396*ce02a71cSSimon Glass }; 397*ce02a71cSSimon Glass 398*ce02a71cSSimon Glass i2cmux { 399*ce02a71cSSimon Glass compatible = "i2c-mux-pinctrl"; 400*ce02a71cSSimon Glass #address-cells = <1>; 401*ce02a71cSSimon Glass #size-cells = <0>; 402*ce02a71cSSimon Glass 403*ce02a71cSSimon Glass i2c-parent = <&{/i2c@7000c400}>; 404*ce02a71cSSimon Glass 405*ce02a71cSSimon Glass pinctrl-names = "ddc", "pta", "idle"; 406*ce02a71cSSimon Glass pinctrl-0 = <&state_i2cmux_ddc>; 407*ce02a71cSSimon Glass pinctrl-1 = <&state_i2cmux_pta>; 408*ce02a71cSSimon Glass pinctrl-2 = <&state_i2cmux_idle>; 409*ce02a71cSSimon Glass 410*ce02a71cSSimon Glass hdmi_ddc: i2c@0 { 411*ce02a71cSSimon Glass reg = <0>; 412*ce02a71cSSimon Glass #address-cells = <1>; 413*ce02a71cSSimon Glass #size-cells = <0>; 414*ce02a71cSSimon Glass }; 415*ce02a71cSSimon Glass 416*ce02a71cSSimon Glass lvds_ddc: i2c@1 { 417*ce02a71cSSimon Glass reg = <1>; 418*ce02a71cSSimon Glass #address-cells = <1>; 419*ce02a71cSSimon Glass #size-cells = <0>; 420*ce02a71cSSimon Glass 421*ce02a71cSSimon Glass smart-battery@b { 422*ce02a71cSSimon Glass compatible = "ti,bq20z75", "smart-battery-1.1"; 423*ce02a71cSSimon Glass reg = <0xb>; 424*ce02a71cSSimon Glass ti,i2c-retry-count = <2>; 425*ce02a71cSSimon Glass ti,poll-retry-count = <10>; 426*ce02a71cSSimon Glass }; 427*ce02a71cSSimon Glass }; 4285ab502cbSMasahiro Yamada }; 4295ab502cbSMasahiro Yamada 4305ab502cbSMasahiro Yamada i2c@7000c500 { 431ee7d755aSSimon Glass status = "okay"; 432*ce02a71cSSimon Glass clock-frequency = <400000>; 433*ce02a71cSSimon Glass }; 434*ce02a71cSSimon Glass 435*ce02a71cSSimon Glass i2c@7000d000 { 436*ce02a71cSSimon Glass status = "okay"; 437*ce02a71cSSimon Glass clock-frequency = <400000>; 438*ce02a71cSSimon Glass 439*ce02a71cSSimon Glass magnetometer@c { 440*ce02a71cSSimon Glass compatible = "asahi-kasei,ak8975"; 441*ce02a71cSSimon Glass reg = <0xc>; 442*ce02a71cSSimon Glass interrupt-parent = <&gpio>; 443*ce02a71cSSimon Glass interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 444*ce02a71cSSimon Glass }; 445*ce02a71cSSimon Glass 446*ce02a71cSSimon Glass pmic: tps6586x@34 { 447*ce02a71cSSimon Glass compatible = "ti,tps6586x"; 448*ce02a71cSSimon Glass reg = <0x34>; 449*ce02a71cSSimon Glass interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 450*ce02a71cSSimon Glass 451*ce02a71cSSimon Glass ti,system-power-controller; 452*ce02a71cSSimon Glass 453*ce02a71cSSimon Glass #gpio-cells = <2>; 454*ce02a71cSSimon Glass gpio-controller; 455*ce02a71cSSimon Glass 456*ce02a71cSSimon Glass sys-supply = <&vdd_5v0_reg>; 457*ce02a71cSSimon Glass vin-sm0-supply = <&sys_reg>; 458*ce02a71cSSimon Glass vin-sm1-supply = <&sys_reg>; 459*ce02a71cSSimon Glass vin-sm2-supply = <&sys_reg>; 460*ce02a71cSSimon Glass vinldo01-supply = <&sm2_reg>; 461*ce02a71cSSimon Glass vinldo23-supply = <&sm2_reg>; 462*ce02a71cSSimon Glass vinldo4-supply = <&sm2_reg>; 463*ce02a71cSSimon Glass vinldo678-supply = <&sm2_reg>; 464*ce02a71cSSimon Glass vinldo9-supply = <&sm2_reg>; 465*ce02a71cSSimon Glass 466*ce02a71cSSimon Glass regulators { 467*ce02a71cSSimon Glass sys_reg: sys { 468*ce02a71cSSimon Glass regulator-name = "vdd_sys"; 469*ce02a71cSSimon Glass regulator-always-on; 470*ce02a71cSSimon Glass }; 471*ce02a71cSSimon Glass 472*ce02a71cSSimon Glass sm0 { 473*ce02a71cSSimon Glass regulator-name = "vdd_sm0,vdd_core"; 474*ce02a71cSSimon Glass regulator-min-microvolt = <1300000>; 475*ce02a71cSSimon Glass regulator-max-microvolt = <1300000>; 476*ce02a71cSSimon Glass regulator-always-on; 477*ce02a71cSSimon Glass }; 478*ce02a71cSSimon Glass 479*ce02a71cSSimon Glass sm1 { 480*ce02a71cSSimon Glass regulator-name = "vdd_sm1,vdd_cpu"; 481*ce02a71cSSimon Glass regulator-min-microvolt = <1125000>; 482*ce02a71cSSimon Glass regulator-max-microvolt = <1125000>; 483*ce02a71cSSimon Glass regulator-always-on; 484*ce02a71cSSimon Glass }; 485*ce02a71cSSimon Glass 486*ce02a71cSSimon Glass sm2_reg: sm2 { 487*ce02a71cSSimon Glass regulator-name = "vdd_sm2,vin_ldo*"; 488*ce02a71cSSimon Glass regulator-min-microvolt = <3700000>; 489*ce02a71cSSimon Glass regulator-max-microvolt = <3700000>; 490*ce02a71cSSimon Glass regulator-always-on; 491*ce02a71cSSimon Glass }; 492*ce02a71cSSimon Glass 493*ce02a71cSSimon Glass /* LDO0 is not connected to anything */ 494*ce02a71cSSimon Glass 495*ce02a71cSSimon Glass ldo1 { 496*ce02a71cSSimon Glass regulator-name = "vdd_ldo1,avdd_pll*"; 497*ce02a71cSSimon Glass regulator-min-microvolt = <1100000>; 498*ce02a71cSSimon Glass regulator-max-microvolt = <1100000>; 499*ce02a71cSSimon Glass regulator-always-on; 500*ce02a71cSSimon Glass }; 501*ce02a71cSSimon Glass 502*ce02a71cSSimon Glass ldo2 { 503*ce02a71cSSimon Glass regulator-name = "vdd_ldo2,vdd_rtc"; 504*ce02a71cSSimon Glass regulator-min-microvolt = <1200000>; 505*ce02a71cSSimon Glass regulator-max-microvolt = <1200000>; 506*ce02a71cSSimon Glass }; 507*ce02a71cSSimon Glass 508*ce02a71cSSimon Glass ldo3 { 509*ce02a71cSSimon Glass regulator-name = "vdd_ldo3,avdd_usb*"; 510*ce02a71cSSimon Glass regulator-min-microvolt = <3300000>; 511*ce02a71cSSimon Glass regulator-max-microvolt = <3300000>; 512*ce02a71cSSimon Glass regulator-always-on; 513*ce02a71cSSimon Glass }; 514*ce02a71cSSimon Glass 515*ce02a71cSSimon Glass ldo4 { 516*ce02a71cSSimon Glass regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 517*ce02a71cSSimon Glass regulator-min-microvolt = <1800000>; 518*ce02a71cSSimon Glass regulator-max-microvolt = <1800000>; 519*ce02a71cSSimon Glass regulator-always-on; 520*ce02a71cSSimon Glass }; 521*ce02a71cSSimon Glass 522*ce02a71cSSimon Glass ldo5 { 523*ce02a71cSSimon Glass regulator-name = "vdd_ldo5,vcore_mmc"; 524*ce02a71cSSimon Glass regulator-min-microvolt = <2850000>; 525*ce02a71cSSimon Glass regulator-max-microvolt = <2850000>; 526*ce02a71cSSimon Glass regulator-always-on; 527*ce02a71cSSimon Glass }; 528*ce02a71cSSimon Glass 529*ce02a71cSSimon Glass ldo6 { 530*ce02a71cSSimon Glass regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 531*ce02a71cSSimon Glass regulator-min-microvolt = <1800000>; 532*ce02a71cSSimon Glass regulator-max-microvolt = <1800000>; 533*ce02a71cSSimon Glass }; 534*ce02a71cSSimon Glass 535*ce02a71cSSimon Glass hdmi_vdd_reg: ldo7 { 536*ce02a71cSSimon Glass regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 537*ce02a71cSSimon Glass regulator-min-microvolt = <3300000>; 538*ce02a71cSSimon Glass regulator-max-microvolt = <3300000>; 539*ce02a71cSSimon Glass }; 540*ce02a71cSSimon Glass 541*ce02a71cSSimon Glass hdmi_pll_reg: ldo8 { 542*ce02a71cSSimon Glass regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 543*ce02a71cSSimon Glass regulator-min-microvolt = <1800000>; 544*ce02a71cSSimon Glass regulator-max-microvolt = <1800000>; 545*ce02a71cSSimon Glass }; 546*ce02a71cSSimon Glass 547*ce02a71cSSimon Glass ldo9 { 548*ce02a71cSSimon Glass regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 549*ce02a71cSSimon Glass regulator-min-microvolt = <2850000>; 550*ce02a71cSSimon Glass regulator-max-microvolt = <2850000>; 551*ce02a71cSSimon Glass regulator-always-on; 552*ce02a71cSSimon Glass }; 553*ce02a71cSSimon Glass 554*ce02a71cSSimon Glass ldo_rtc { 555*ce02a71cSSimon Glass regulator-name = "vdd_rtc_out,vdd_cell"; 556*ce02a71cSSimon Glass regulator-min-microvolt = <3300000>; 557*ce02a71cSSimon Glass regulator-max-microvolt = <3300000>; 558*ce02a71cSSimon Glass regulator-always-on; 559*ce02a71cSSimon Glass }; 560*ce02a71cSSimon Glass }; 561*ce02a71cSSimon Glass }; 562*ce02a71cSSimon Glass 563*ce02a71cSSimon Glass temperature-sensor@4c { 564*ce02a71cSSimon Glass compatible = "onnn,nct1008"; 565*ce02a71cSSimon Glass reg = <0x4c>; 566*ce02a71cSSimon Glass }; 5675ab502cbSMasahiro Yamada }; 5685ab502cbSMasahiro Yamada 5695ab502cbSMasahiro Yamada kbc@7000e200 { 570ee7d755aSSimon Glass status = "okay"; 571*ce02a71cSSimon Glass nvidia,debounce-delay-ms = <32>; 572*ce02a71cSSimon Glass nvidia,repeat-delay-ms = <160>; 573*ce02a71cSSimon Glass nvidia,ghost-filter; 574*ce02a71cSSimon Glass nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 575*ce02a71cSSimon Glass nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; 576*ce02a71cSSimon Glass linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) 577*ce02a71cSSimon Glass MATRIX_KEY(0x00, 0x03, KEY_S) 578*ce02a71cSSimon Glass MATRIX_KEY(0x00, 0x04, KEY_A) 579*ce02a71cSSimon Glass MATRIX_KEY(0x00, 0x05, KEY_Z) 580*ce02a71cSSimon Glass MATRIX_KEY(0x00, 0x07, KEY_FN) 581*ce02a71cSSimon Glass 582*ce02a71cSSimon Glass MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) 583*ce02a71cSSimon Glass MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) 584*ce02a71cSSimon Glass MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) 585*ce02a71cSSimon Glass 586*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x00, KEY_5) 587*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x01, KEY_4) 588*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x02, KEY_R) 589*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x03, KEY_E) 590*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x04, KEY_F) 591*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x05, KEY_D) 592*ce02a71cSSimon Glass MATRIX_KEY(0x03, 0x06, KEY_X) 593*ce02a71cSSimon Glass 594*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x00, KEY_7) 595*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x01, KEY_6) 596*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x02, KEY_T) 597*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x03, KEY_H) 598*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x04, KEY_G) 599*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x05, KEY_V) 600*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x06, KEY_C) 601*ce02a71cSSimon Glass MATRIX_KEY(0x04, 0x07, KEY_SPACE) 602*ce02a71cSSimon Glass 603*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x00, KEY_9) 604*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x01, KEY_8) 605*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x02, KEY_U) 606*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x03, KEY_Y) 607*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x04, KEY_J) 608*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x05, KEY_N) 609*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x06, KEY_B) 610*ce02a71cSSimon Glass MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) 611*ce02a71cSSimon Glass 612*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x00, KEY_MINUS) 613*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x01, KEY_0) 614*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x02, KEY_O) 615*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x03, KEY_I) 616*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x04, KEY_L) 617*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x05, KEY_K) 618*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x06, KEY_COMMA) 619*ce02a71cSSimon Glass MATRIX_KEY(0x06, 0x07, KEY_M) 620*ce02a71cSSimon Glass 621*ce02a71cSSimon Glass MATRIX_KEY(0x07, 0x01, KEY_EQUAL) 622*ce02a71cSSimon Glass MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) 623*ce02a71cSSimon Glass MATRIX_KEY(0x07, 0x03, KEY_ENTER) 624*ce02a71cSSimon Glass MATRIX_KEY(0x07, 0x07, KEY_MENU) 625*ce02a71cSSimon Glass 626*ce02a71cSSimon Glass MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) 627*ce02a71cSSimon Glass MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) 628*ce02a71cSSimon Glass 629*ce02a71cSSimon Glass MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) 630*ce02a71cSSimon Glass MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) 631*ce02a71cSSimon Glass 632*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) 633*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x01, KEY_P) 634*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) 635*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) 636*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x04, KEY_SLASH) 637*ce02a71cSSimon Glass MATRIX_KEY(0x0B, 0x05, KEY_DOT) 638*ce02a71cSSimon Glass 639*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x00, KEY_F10) 640*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x01, KEY_F9) 641*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) 642*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x03, KEY_3) 643*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x04, KEY_2) 644*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x05, KEY_UP) 645*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x06, KEY_PRINT) 646*ce02a71cSSimon Glass MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) 647*ce02a71cSSimon Glass 648*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x00, KEY_INSERT) 649*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x01, KEY_DELETE) 650*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) 651*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) 652*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) 653*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x06, KEY_DOWN) 654*ce02a71cSSimon Glass MATRIX_KEY(0x0D, 0x07, KEY_LEFT) 655*ce02a71cSSimon Glass 656*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x00, KEY_F11) 657*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x01, KEY_F12) 658*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x02, KEY_F8) 659*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x03, KEY_Q) 660*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x04, KEY_F4) 661*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x05, KEY_F3) 662*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x06, KEY_1) 663*ce02a71cSSimon Glass MATRIX_KEY(0x0E, 0x07, KEY_F7) 664*ce02a71cSSimon Glass 665*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x00, KEY_ESC) 666*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) 667*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x02, KEY_F5) 668*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x03, KEY_TAB) 669*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x04, KEY_F1) 670*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x05, KEY_F2) 671*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) 672*ce02a71cSSimon Glass MATRIX_KEY(0x0F, 0x07, KEY_F6) 673*ce02a71cSSimon Glass 674*ce02a71cSSimon Glass /* Software Handled Function Keys */ 675*ce02a71cSSimon Glass MATRIX_KEY(0x14, 0x00, KEY_KP7) 676*ce02a71cSSimon Glass 677*ce02a71cSSimon Glass MATRIX_KEY(0x15, 0x00, KEY_KP9) 678*ce02a71cSSimon Glass MATRIX_KEY(0x15, 0x01, KEY_KP8) 679*ce02a71cSSimon Glass MATRIX_KEY(0x15, 0x02, KEY_KP4) 680*ce02a71cSSimon Glass MATRIX_KEY(0x15, 0x04, KEY_KP1) 681*ce02a71cSSimon Glass 682*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) 683*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x02, KEY_KP6) 684*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x03, KEY_KP5) 685*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x04, KEY_KP3) 686*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x05, KEY_KP2) 687*ce02a71cSSimon Glass MATRIX_KEY(0x16, 0x07, KEY_KP0) 688*ce02a71cSSimon Glass 689*ce02a71cSSimon Glass MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) 690*ce02a71cSSimon Glass MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) 691*ce02a71cSSimon Glass MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) 692*ce02a71cSSimon Glass MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) 693*ce02a71cSSimon Glass 694*ce02a71cSSimon Glass MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) 695*ce02a71cSSimon Glass 696*ce02a71cSSimon Glass MATRIX_KEY(0x1D, 0x03, KEY_HOME) 697*ce02a71cSSimon Glass MATRIX_KEY(0x1D, 0x04, KEY_END) 698*ce02a71cSSimon Glass MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) 699*ce02a71cSSimon Glass MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) 700*ce02a71cSSimon Glass MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) 701*ce02a71cSSimon Glass 702*ce02a71cSSimon Glass MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) 703*ce02a71cSSimon Glass MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) 704*ce02a71cSSimon Glass MATRIX_KEY(0x1E, 0x02, KEY_MUTE) 705*ce02a71cSSimon Glass 706*ce02a71cSSimon Glass MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; 7075ab502cbSMasahiro Yamada }; 7085ab502cbSMasahiro Yamada 709*ce02a71cSSimon Glass pmc@7000e400 { 710*ce02a71cSSimon Glass nvidia,invert-interrupt; 711*ce02a71cSSimon Glass nvidia,suspend-mode = <1>; 712*ce02a71cSSimon Glass nvidia,cpu-pwr-good-time = <5000>; 713*ce02a71cSSimon Glass nvidia,cpu-pwr-off-time = <5000>; 714*ce02a71cSSimon Glass nvidia,core-pwr-good-time = <3845 3845>; 715*ce02a71cSSimon Glass nvidia,core-pwr-off-time = <3875>; 716*ce02a71cSSimon Glass nvidia,sys-clock-req-active-high; 717*ce02a71cSSimon Glass }; 718*ce02a71cSSimon Glass 719*ce02a71cSSimon Glass memory-controller@7000f400 { 7205ab502cbSMasahiro Yamada emc-table@190000 { 7215ab502cbSMasahiro Yamada reg = <190000>; 7225ab502cbSMasahiro Yamada compatible = "nvidia,tegra20-emc-table"; 7235ab502cbSMasahiro Yamada clock-frequency = <190000>; 7245ab502cbSMasahiro Yamada nvidia,emc-registers = <0x0000000c 0x00000026 7255ab502cbSMasahiro Yamada 0x00000009 0x00000003 0x00000004 0x00000004 7265ab502cbSMasahiro Yamada 0x00000002 0x0000000c 0x00000003 0x00000003 7275ab502cbSMasahiro Yamada 0x00000002 0x00000001 0x00000004 0x00000005 7285ab502cbSMasahiro Yamada 0x00000004 0x00000009 0x0000000d 0x0000059f 7295ab502cbSMasahiro Yamada 0x00000000 0x00000003 0x00000003 0x00000003 7305ab502cbSMasahiro Yamada 0x00000003 0x00000001 0x0000000b 0x000000c8 7315ab502cbSMasahiro Yamada 0x00000003 0x00000007 0x00000004 0x0000000f 7325ab502cbSMasahiro Yamada 0x00000002 0x00000000 0x00000000 0x00000002 7335ab502cbSMasahiro Yamada 0x00000000 0x00000000 0x00000083 0xa06204ae 7345ab502cbSMasahiro Yamada 0x007dc010 0x00000000 0x00000000 0x00000000 7355ab502cbSMasahiro Yamada 0x00000000 0x00000000 0x00000000 0x00000000>; 7365ab502cbSMasahiro Yamada }; 737*ce02a71cSSimon Glass 7385ab502cbSMasahiro Yamada emc-table@380000 { 7395ab502cbSMasahiro Yamada reg = <380000>; 7405ab502cbSMasahiro Yamada compatible = "nvidia,tegra20-emc-table"; 7415ab502cbSMasahiro Yamada clock-frequency = <380000>; 7425ab502cbSMasahiro Yamada nvidia,emc-registers = <0x00000017 0x0000004b 7435ab502cbSMasahiro Yamada 0x00000012 0x00000006 0x00000004 0x00000005 7445ab502cbSMasahiro Yamada 0x00000003 0x0000000c 0x00000006 0x00000006 7455ab502cbSMasahiro Yamada 0x00000003 0x00000001 0x00000004 0x00000005 7465ab502cbSMasahiro Yamada 0x00000004 0x00000009 0x0000000d 0x00000b5f 7475ab502cbSMasahiro Yamada 0x00000000 0x00000003 0x00000003 0x00000006 7485ab502cbSMasahiro Yamada 0x00000006 0x00000001 0x00000011 0x000000c8 7495ab502cbSMasahiro Yamada 0x00000003 0x0000000e 0x00000007 0x0000000f 7505ab502cbSMasahiro Yamada 0x00000002 0x00000000 0x00000000 0x00000002 7515ab502cbSMasahiro Yamada 0x00000000 0x00000000 0x00000083 0xe044048b 7525ab502cbSMasahiro Yamada 0x007d8010 0x00000000 0x00000000 0x00000000 7535ab502cbSMasahiro Yamada 0x00000000 0x00000000 0x00000000 0x00000000>; 7545ab502cbSMasahiro Yamada }; 7555ab502cbSMasahiro Yamada }; 7565ab502cbSMasahiro Yamada 7575ab502cbSMasahiro Yamada usb@c5000000 { 758ee7d755aSSimon Glass status = "okay"; 7592b2b50bcSSimon Glass nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 7605ab502cbSMasahiro Yamada dr_mode = "otg"; 7615ab502cbSMasahiro Yamada }; 7625ab502cbSMasahiro Yamada 763*ce02a71cSSimon Glass usb-phy@c5000000 { 764*ce02a71cSSimon Glass status = "okay"; 765*ce02a71cSSimon Glass vbus-supply = <&vbus_reg>; 766*ce02a71cSSimon Glass dr_mode = "otg"; 767*ce02a71cSSimon Glass }; 768*ce02a71cSSimon Glass 7695ab502cbSMasahiro Yamada usb@c5004000 { 7705ab502cbSMasahiro Yamada status = "disabled"; 771*ce02a71cSSimon Glass nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 772*ce02a71cSSimon Glass GPIO_ACTIVE_LOW>; 773*ce02a71cSSimon Glass }; 774*ce02a71cSSimon Glass 775*ce02a71cSSimon Glass usb-phy@c5004000 { 776*ce02a71cSSimon Glass status = "okay"; 777*ce02a71cSSimon Glass nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 778*ce02a71cSSimon Glass GPIO_ACTIVE_LOW>; 7795ab502cbSMasahiro Yamada }; 7805ab502cbSMasahiro Yamada 781ee7d755aSSimon Glass usb@c5008000 { 782ee7d755aSSimon Glass status = "okay"; 783ee7d755aSSimon Glass }; 784ee7d755aSSimon Glass 785*ce02a71cSSimon Glass usb-phy@c5008000 { 786*ce02a71cSSimon Glass status = "okay"; 787*ce02a71cSSimon Glass }; 788*ce02a71cSSimon Glass 789*ce02a71cSSimon Glass sdhci@c8000000 { 790*ce02a71cSSimon Glass status = "okay"; 791*ce02a71cSSimon Glass power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 792*ce02a71cSSimon Glass bus-width = <4>; 793*ce02a71cSSimon Glass keep-power-in-suspend; 794*ce02a71cSSimon Glass }; 795*ce02a71cSSimon Glass 7965ab502cbSMasahiro Yamada sdhci@c8000400 { 7975ab502cbSMasahiro Yamada status = "okay"; 7982b2b50bcSSimon Glass cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 7992b2b50bcSSimon Glass wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 8002b2b50bcSSimon Glass power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 8015ab502cbSMasahiro Yamada bus-width = <4>; 8025ab502cbSMasahiro Yamada }; 8035ab502cbSMasahiro Yamada 8045ab502cbSMasahiro Yamada sdhci@c8000600 { 8055ab502cbSMasahiro Yamada status = "okay"; 8065ab502cbSMasahiro Yamada bus-width = <8>; 807*ce02a71cSSimon Glass non-removable; 808*ce02a71cSSimon Glass }; 809*ce02a71cSSimon Glass 810*ce02a71cSSimon Glass backlight: backlight { 811*ce02a71cSSimon Glass compatible = "pwm-backlight"; 812*ce02a71cSSimon Glass 813*ce02a71cSSimon Glass enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 814*ce02a71cSSimon Glass power-supply = <&vdd_bl_reg>; 815*ce02a71cSSimon Glass pwms = <&pwm 2 5000000>; 816*ce02a71cSSimon Glass 817*ce02a71cSSimon Glass brightness-levels = <0 4 8 16 32 64 128 255>; 818*ce02a71cSSimon Glass default-brightness-level = <6>; 8195ab502cbSMasahiro Yamada }; 8205ab502cbSMasahiro Yamada 821ee7d755aSSimon Glass clocks { 822ee7d755aSSimon Glass compatible = "simple-bus"; 823ee7d755aSSimon Glass #address-cells = <1>; 824ee7d755aSSimon Glass #size-cells = <0>; 825ee7d755aSSimon Glass 826ee7d755aSSimon Glass clk32k_in: clock@0 { 827ee7d755aSSimon Glass compatible = "fixed-clock"; 828ee7d755aSSimon Glass reg=<0>; 829ee7d755aSSimon Glass #clock-cells = <0>; 830ee7d755aSSimon Glass clock-frequency = <32768>; 831ee7d755aSSimon Glass }; 832ee7d755aSSimon Glass }; 833ee7d755aSSimon Glass 834*ce02a71cSSimon Glass gpio-keys { 835*ce02a71cSSimon Glass compatible = "gpio-keys"; 836*ce02a71cSSimon Glass 837*ce02a71cSSimon Glass power { 838*ce02a71cSSimon Glass label = "Power"; 839*ce02a71cSSimon Glass gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 840*ce02a71cSSimon Glass linux,code = <KEY_POWER>; 841*ce02a71cSSimon Glass gpio-key,wakeup; 84291c08afeSSimon Glass }; 84391c08afeSSimon Glass 844*ce02a71cSSimon Glass lid { 845*ce02a71cSSimon Glass label = "Lid"; 846*ce02a71cSSimon Glass gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; 847*ce02a71cSSimon Glass linux,input-type = <5>; /* EV_SW */ 848*ce02a71cSSimon Glass linux,code = <0>; /* SW_LID */ 849*ce02a71cSSimon Glass debounce-interval = <1>; 850*ce02a71cSSimon Glass gpio-key,wakeup; 851*ce02a71cSSimon Glass }; 852*ce02a71cSSimon Glass }; 853*ce02a71cSSimon Glass 854*ce02a71cSSimon Glass panel: panel { 8555ab502cbSMasahiro Yamada /* Seaboard has 1366x768 */ 8565ab502cbSMasahiro Yamada clock = <70600000>; 8575ab502cbSMasahiro Yamada xres = <1366>; 8585ab502cbSMasahiro Yamada yres = <768>; 8595ab502cbSMasahiro Yamada left-margin = <58>; 8605ab502cbSMasahiro Yamada right-margin = <58>; 8615ab502cbSMasahiro Yamada hsync-len = <58>; 8625ab502cbSMasahiro Yamada lower-margin = <4>; 8635ab502cbSMasahiro Yamada upper-margin = <4>; 8645ab502cbSMasahiro Yamada vsync-len = <4>; 8655ab502cbSMasahiro Yamada hsync-active-high; 8665ab502cbSMasahiro Yamada nvidia,bits-per-pixel = <16>; 8675ab502cbSMasahiro Yamada nvidia,pwm = <&pwm 2 0>; 8682b2b50bcSSimon Glass nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) 8692b2b50bcSSimon Glass GPIO_ACTIVE_HIGH>; 8702b2b50bcSSimon Glass nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) 8712b2b50bcSSimon Glass GPIO_ACTIVE_HIGH>; 8722b2b50bcSSimon Glass nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) 8732b2b50bcSSimon Glass GPIO_ACTIVE_HIGH>; 8742b2b50bcSSimon Glass nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) 8752b2b50bcSSimon Glass GPIO_ACTIVE_HIGH>; 8765ab502cbSMasahiro Yamada nvidia,panel-timings = <400 4 203 17 15>; 8775ab502cbSMasahiro Yamada }; 878*ce02a71cSSimon Glass 879*ce02a71cSSimon Glass regulators { 880*ce02a71cSSimon Glass compatible = "simple-bus"; 881*ce02a71cSSimon Glass #address-cells = <1>; 882*ce02a71cSSimon Glass #size-cells = <0>; 883*ce02a71cSSimon Glass 884*ce02a71cSSimon Glass vdd_5v0_reg: regulator@0 { 885*ce02a71cSSimon Glass compatible = "regulator-fixed"; 886*ce02a71cSSimon Glass reg = <0>; 887*ce02a71cSSimon Glass regulator-name = "vdd_5v0"; 888*ce02a71cSSimon Glass regulator-min-microvolt = <5000000>; 889*ce02a71cSSimon Glass regulator-max-microvolt = <5000000>; 890*ce02a71cSSimon Glass regulator-always-on; 891*ce02a71cSSimon Glass }; 892*ce02a71cSSimon Glass 893*ce02a71cSSimon Glass regulator@1 { 894*ce02a71cSSimon Glass compatible = "regulator-fixed"; 895*ce02a71cSSimon Glass reg = <1>; 896*ce02a71cSSimon Glass regulator-name = "vdd_1v5"; 897*ce02a71cSSimon Glass regulator-min-microvolt = <1500000>; 898*ce02a71cSSimon Glass regulator-max-microvolt = <1500000>; 899*ce02a71cSSimon Glass gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 900*ce02a71cSSimon Glass }; 901*ce02a71cSSimon Glass 902*ce02a71cSSimon Glass regulator@2 { 903*ce02a71cSSimon Glass compatible = "regulator-fixed"; 904*ce02a71cSSimon Glass reg = <2>; 905*ce02a71cSSimon Glass regulator-name = "vdd_1v2"; 906*ce02a71cSSimon Glass regulator-min-microvolt = <1200000>; 907*ce02a71cSSimon Glass regulator-max-microvolt = <1200000>; 908*ce02a71cSSimon Glass gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 909*ce02a71cSSimon Glass enable-active-high; 910*ce02a71cSSimon Glass }; 911*ce02a71cSSimon Glass 912*ce02a71cSSimon Glass vbus_reg: regulator@3 { 913*ce02a71cSSimon Glass compatible = "regulator-fixed"; 914*ce02a71cSSimon Glass reg = <3>; 915*ce02a71cSSimon Glass regulator-name = "vdd_vbus_wup1"; 916*ce02a71cSSimon Glass regulator-min-microvolt = <5000000>; 917*ce02a71cSSimon Glass regulator-max-microvolt = <5000000>; 918*ce02a71cSSimon Glass enable-active-high; 919*ce02a71cSSimon Glass gpio = <&gpio TEGRA_GPIO(D, 0) 0>; 920*ce02a71cSSimon Glass regulator-always-on; 921*ce02a71cSSimon Glass regulator-boot-on; 922*ce02a71cSSimon Glass }; 923*ce02a71cSSimon Glass 924*ce02a71cSSimon Glass vdd_pnl_reg: regulator@4 { 925*ce02a71cSSimon Glass compatible = "regulator-fixed"; 926*ce02a71cSSimon Glass reg = <4>; 927*ce02a71cSSimon Glass regulator-name = "vdd_pnl"; 928*ce02a71cSSimon Glass regulator-min-microvolt = <2800000>; 929*ce02a71cSSimon Glass regulator-max-microvolt = <2800000>; 930*ce02a71cSSimon Glass gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 931*ce02a71cSSimon Glass enable-active-high; 932*ce02a71cSSimon Glass }; 933*ce02a71cSSimon Glass 934*ce02a71cSSimon Glass vdd_bl_reg: regulator@5 { 935*ce02a71cSSimon Glass compatible = "regulator-fixed"; 936*ce02a71cSSimon Glass reg = <5>; 937*ce02a71cSSimon Glass regulator-name = "vdd_bl"; 938*ce02a71cSSimon Glass regulator-min-microvolt = <2800000>; 939*ce02a71cSSimon Glass regulator-max-microvolt = <2800000>; 940*ce02a71cSSimon Glass gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 941*ce02a71cSSimon Glass enable-active-high; 942*ce02a71cSSimon Glass }; 943*ce02a71cSSimon Glass 944*ce02a71cSSimon Glass vdd_hdmi: regulator@6 { 945*ce02a71cSSimon Glass compatible = "regulator-fixed"; 946*ce02a71cSSimon Glass reg = <6>; 947*ce02a71cSSimon Glass regulator-name = "VDDIO_HDMI"; 948*ce02a71cSSimon Glass regulator-min-microvolt = <5000000>; 949*ce02a71cSSimon Glass regulator-max-microvolt = <5000000>; 950*ce02a71cSSimon Glass gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 951*ce02a71cSSimon Glass enable-active-high; 952*ce02a71cSSimon Glass vin-supply = <&vdd_5v0_reg>; 953*ce02a71cSSimon Glass }; 954*ce02a71cSSimon Glass }; 955*ce02a71cSSimon Glass 956*ce02a71cSSimon Glass sound { 957*ce02a71cSSimon Glass compatible = "nvidia,tegra-audio-wm8903-seaboard", 958*ce02a71cSSimon Glass "nvidia,tegra-audio-wm8903"; 959*ce02a71cSSimon Glass nvidia,model = "NVIDIA Tegra Seaboard"; 960*ce02a71cSSimon Glass 961*ce02a71cSSimon Glass nvidia,audio-routing = 962*ce02a71cSSimon Glass "Headphone Jack", "HPOUTR", 963*ce02a71cSSimon Glass "Headphone Jack", "HPOUTL", 964*ce02a71cSSimon Glass "Int Spk", "ROP", 965*ce02a71cSSimon Glass "Int Spk", "RON", 966*ce02a71cSSimon Glass "Int Spk", "LOP", 967*ce02a71cSSimon Glass "Int Spk", "LON", 968*ce02a71cSSimon Glass "Mic Jack", "MICBIAS", 969*ce02a71cSSimon Glass "IN1R", "Mic Jack"; 970*ce02a71cSSimon Glass 971*ce02a71cSSimon Glass nvidia,i2s-controller = <&tegra_i2s1>; 972*ce02a71cSSimon Glass nvidia,audio-codec = <&wm8903>; 973*ce02a71cSSimon Glass 974*ce02a71cSSimon Glass nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 975*ce02a71cSSimon Glass nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; 976*ce02a71cSSimon Glass 977*ce02a71cSSimon Glass clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 978*ce02a71cSSimon Glass <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 979*ce02a71cSSimon Glass <&tegra_car TEGRA20_CLK_CDEV1>; 980*ce02a71cSSimon Glass clock-names = "pll_a", "pll_a_out0", "mclk"; 981*ce02a71cSSimon Glass }; 9825ab502cbSMasahiro Yamada}; 983