xref: /openbmc/u-boot/arch/arm/dts/stm32f746.dtsi (revision d33a6a2f064a5dabfc277d5345aa03a9fbce4680)

/*
 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
 *
 * Based on:
 * stm32f429.dtsi from Linux
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
};

	soc {
		u-boot,dm-pre-reloc;
		mac: ethernet@40028000 {
			compatible = "st,stm32-dwmac";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			interrupts = <61>, <62>;
			interrupt-names = "macirq", "eth_wake_irq";
			snps,pbl = <8>;
			snps,mixed-burst;
			dma-ranges;
			status = "disabled";
		};

		fmc: fmc@A0000000 {
			compatible = "st,stm32-fmc";
			reg = <0xA0000000 0x1000>;
			clocks = <&rcc 0 64>;
			u-boot,dm-pre-reloc;
		};

		qspi: quadspi@A0001000 {
			compatible = "st,stm32-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <92>;
			spi-max-frequency = <108000000>;
			clocks = <&rcc 0 65>;
			status = "disabled";
		};
		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 164>;
			status = "disabled";
			u-boot,dm-pre-reloc;
		};
		rcc: rcc@40023810 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
			u-boot,dm-pre-reloc;
		};

		pinctrl: pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f746-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			u-boot,dm-pre-reloc;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x0 0x400>;
				clocks = <&rcc 0 0>;
				st,bank-name = "GPIOA";
				u-boot,dm-pre-reloc;
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x400 0x400>;
				clocks = <&rcc 0 1>;
				st,bank-name = "GPIOB";
				u-boot,dm-pre-reloc;
			};


			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x800 0x400>;
				clocks = <&rcc 0 2>;
				st,bank-name = "GPIOC";
				u-boot,dm-pre-reloc;
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 3>;
				st,bank-name = "GPIOD";
				u-boot,dm-pre-reloc;
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 4>;
				st,bank-name = "GPIOE";
				u-boot,dm-pre-reloc;
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 5>;
				st,bank-name = "GPIOF";
				u-boot,dm-pre-reloc;
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 6>;
				st,bank-name = "GPIOG";
				u-boot,dm-pre-reloc;
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 7>;
				st,bank-name = "GPIOH";
				u-boot,dm-pre-reloc;
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 8>;
				st,bank-name = "GPIOI";
				u-boot,dm-pre-reloc;
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 9>;
				st,bank-name = "GPIOJ";
				u-boot,dm-pre-reloc;
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 10>;
				st,bank-name = "GPIOK";
				u-boot,dm-pre-reloc;
			};

			usart1_pins_a: usart1@0 {
				pins1 {
					pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
				pins2 {
					pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
					bias-disable;
				};
			};
			ethernet_mii: mii@0 {
				pins {
					pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
						 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
						 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
						 <STM32F746_PA2_FUNC_ETH_MDIO>,
						 <STM32F746_PC1_FUNC_ETH_MDC>,
						 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
						 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
						 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
						 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
					slew-rate = <2>;
				};
			};
			qspi_pins: qspi@0{
				pins {
					pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
						 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
						 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
						 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
						 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
						 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
					slew-rate = <2>;
				};
			};

			fmc_pins: fmc@0 {
				pins {
					pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
						 <STM32F746_PD9_FUNC_FMC_D14>,
						 <STM32F746_PD8_FUNC_FMC_D13>,
						 <STM32F746_PE15_FUNC_FMC_D12>,
						 <STM32F746_PE14_FUNC_FMC_D11>,
						 <STM32F746_PE13_FUNC_FMC_D10>,
						 <STM32F746_PE12_FUNC_FMC_D9>,
						 <STM32F746_PE11_FUNC_FMC_D8>,
						 <STM32F746_PE10_FUNC_FMC_D7>,
						 <STM32F746_PE9_FUNC_FMC_D6>,
						 <STM32F746_PE8_FUNC_FMC_D5>,
						 <STM32F746_PE7_FUNC_FMC_D4>,
						 <STM32F746_PD1_FUNC_FMC_D3>,
						 <STM32F746_PD0_FUNC_FMC_D2>,
						 <STM32F746_PD15_FUNC_FMC_D1>,
						 <STM32F746_PD14_FUNC_FMC_D0>,

						 <STM32F746_PE1_FUNC_FMC_NBL1>,
						 <STM32F746_PE0_FUNC_FMC_NBL0>,

						 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
						 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,

						 <STM32F746_PG1_FUNC_FMC_A11>,
						 <STM32F746_PG0_FUNC_FMC_A10>,
						 <STM32F746_PF15_FUNC_FMC_A9>,
						 <STM32F746_PF14_FUNC_FMC_A8>,
						 <STM32F746_PF13_FUNC_FMC_A7>,
						 <STM32F746_PF12_FUNC_FMC_A6>,
						 <STM32F746_PF5_FUNC_FMC_A5>,
						 <STM32F746_PF4_FUNC_FMC_A4>,
						 <STM32F746_PF3_FUNC_FMC_A3>,
						 <STM32F746_PF2_FUNC_FMC_A2>,
						 <STM32F746_PF1_FUNC_FMC_A1>,
						 <STM32F746_PF0_FUNC_FMC_A0>,

						 <STM32F746_PH3_FUNC_FMC_SDNE0>,
						 <STM32F746_PH5_FUNC_FMC_SDNWE>,
						 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
						 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
						 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
						 <STM32F746_PG8_FUNC_FMC_SDCLK>;
					slew-rate = <2>;
				};
			};

		};
	};
};

&systick {
	status = "okay";
};